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VLSI Design
Volume 2, Issue 3, Pages 199-207
http://dx.doi.org/10.1155/1994/71941

An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits

The Bradley Department of Electrical Engineering, Virginia Polytechnic Institute, State University, Blacksburg 24061, Virginia, USA

Received 15 November 1990; Revised 8 March 1991

Copyright © 1994 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Hyung K. Lee and Dong S. Ha, “An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits,” VLSI Design, vol. 2, no. 3, pp. 199-207, 1994. https://doi.org/10.1155/1994/71941.