Digital Hardware TestingView this Special Issue
Optimal Testing and Design of Adders
On-the-fly calculations of area and performance are a typical part of the computer-aided iterative design process in VLSI, which aims at a satisfactory tradeoff of various conflicting objectives, among which are test-generation time and test-set size. However, determining test sets on-the-fly as one circuit is transformed into another is extremely difficult. Our goal is to add a test dimension to the design optimization process that complements methods concerned with area and performance optimization. We define a set of logic transformations that result in easily computed changes to test sets. Test-set preserving (TSP) transformations preserve a combinational circuit’s test sets, while test-set altering (TSA) transformations introduce a minimum number of tests needed to maintain completeness. We illustrate our approach with a family of adders that share area-efficient tree structures and differ in the amount of carry-lookahead used to accelerate carry computation. Members include the ripple-carry adder, which has no lookahead, and the standard carry-lookahead adder, which exploits lookahead across all inputs. It is straightforward to derive area and performance measures for this class of adders. Given an n-bit adder with lookahead degree k, we determine a sequence of circuit transformations that produce the adder of degree k2 and test sets of minimum size. Optimal test sets of size k(logkn + 1) + 2 result for arbitrary n and k, which improve significantly upon previously reported tests.
Copyright © 1994 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.