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VLSI Design
Volume 2, Issue 3, Pages 241-257
http://dx.doi.org/10.1155/1994/80287

SEGMA: A Simulated Evolution Gate-Matrix Layout Algorithm

Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, WI 53706, USA

Received 3 December 1992; Revised 17 March 1993

Copyright © 1994 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Chi-Yu Mao and Yu Hen Hu, “SEGMA: A Simulated Evolution Gate-Matrix Layout Algorithm,” VLSI Design, vol. 2, no. 3, pp. 241-257, 1994. https://doi.org/10.1155/1994/80287.