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VLSI Design
Volume 4, Issue 3, Pages 217-229

Switch-level Differential Fault Simulation of MOS VLSI Circuits

1AT&T Bell Laboratories, 600 Mountain Avenue, Murray Hill 07974, NJ, USA
2Electrical Engineering Department, University of Minnesota, Minneapolis 55455, MN, USA

Copyright © 1996 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A new switch-level fault simulation method for MOS circuits is presented that combines compiled switch-level simulation techniques and functional fault modeling of transistor faults with the new fault simulation algorithm of differential fault simulation. The fault simulator models both node stuck-at-0, stuck-at-1 faults and transistor stuck-on, stuck-open faults. Prior to simulation, the switch-level circuit components are compiled into functional models. The effect of transistor faults on the function of the circuit components is modeled by functional fault models that execute very fast during simulation. Every compiled circuit component is assigned a dominance attribute, which abstracts relative strength information in the circuit. Dominance is used during simulation to resolve the X-state due to fighting pull-up and pull-down transistor paths and also to deduce transistor fault detectability and fault equivalencies prior to simulation. The differential fault simulation algorithm developed for gate-level circuits is adapted for use at the switch-level. Differential fault simulation provides excellent performance with minimum memory requirements, although it incurs a higher overhead at the switch-level than at the gate-level due to the dynamic memory properties of MOS circuits.