Table of Contents
VLSI Design
Volume 4, Issue 3, Pages 149-165

PGEN: A Novel Approach to Sequential Circuit Test Generation

1Department of Computer Science and Information Engineering, National Chung-Cheng University, Chiayi, Taiwan
2Department of Computer Science, New Mexico Tech, Socorro, NM 87801, USA
3Department of Computer Science, Bloomsburg University, Bloomsburg, PA 17815, USA
4Department of Electrical Engineering, University of Ottawa, Ottawa ON K1N 6N5, Canada
5Information Technology Services, AT & T Universal Card Services, Jacksonville, FL 32220, USA

Copyright © 1996 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A novel approach, called PGEN, is proposed to generate test patterns for resettable or nonresettable synchronous sequential circuits. PGEN contains two major routines, Sequential PODEM (S-PODEM) and a differential fault simulator. Given a fault, S-PODEM uses the concept of multiple time compression supported by a pulsating model, and generates a test vector in a single (yet compressed) time frame. Logic simulation (included in S-PODEM) is invoked to expand the single test vector into a test sequence. The single test vector generation methodology and logic simulation are well coordinated and significantly facilitate sequential circuit test generation. A modified version of differential fault simulation is also implemented and included in PGEN to cover other faults detected by the expanded test sequence. Experiments using computer simulation have been conducted, and results are quite satisfactory.