Table of Contents
VLSI Design
Volume 4, Issue 3, Pages 181-197
http://dx.doi.org/10.1155/1996/72136

HYSIM: Hybrid Fault Simulation for Synchronous Sequential Circuits

Department of Electrical and Computer Engineering, University of Wisconsin—Madison, 1415 Johnson Drive, Madison, WI 53706-1691, USA

Copyright © 1996 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

The paper identifies the inefficiencies of the critical processes in concurrent fault simulation and proposes methods to remove such inefficiencies in a systematic manner. Also, proposed are dynamic memory usage reduction strategies for concurrent fault simulators. Through extensive step-by-step experimentation, we verified the effectiveness of the proposed methods for performance improvement and identified best memory management strategy for dynamic memory usage reduction. A simulator, HySim, based on the proposed methods is implemented and shown to outperform the existing fault simulators and achieve dramatic memory usage reduction. The HySim maintains fault lists which are subsets of that of a conventional concurrent fault simulator, which yields shorter fault list processing time and reduced dynamic memory usage. It also employs Release-and-Reconstruct method for fault list construction, where any fault list identified to be useless is released immediately. The experimental results show that Release-and-Reconstruct method is very effective in dynamic memory usage reduction.