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VLSI Design
Volume 4 (1996), Issue 3, Pages 257-269

A Methodology for Testing Arbitrary Bilateral Bit-Level Systolic Arrays

1School of Computer Science, University of Windsor, Windsor, Ontario, N9B 3P4, Canada
2Department of Computer Science, University of South Carolina, Columbia 29208, SC, USA
3Electronics Unit, Indian Statistical Institute, Calcutta 700 035, India

Copyright © 1996 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


In this paper, we discuss the controllability and observability issues in bilateral bit-level systolic arrays. We have introduced a new concept—‘Sj-controllability in M steps’, which is somewhat analogous to the concept of C-testability and refers to the fact that all the cells in the array can be set to the state Sj in at most M steps after initialization. Systolic arrays where the value of M is independent of the length, of the array are characterized. Our testing procedure is based on partitioning the array into several identical subarrays which allows us to apply a repetitive pattern of tests and propagate test outcome to the observable extremities so that every cell in the array is tested by a minimum sequence of tests. Based on this concept,we have developed a set of sufficient conditions for an arbitrary bilateral bit-level systolic array to be testable for single faults.