VLSI Design

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Volume 12 |Article ID 032515 | https://doi.org/10.1155/2001/32515

Jacob Savir, "BIST-Based Fault Diagnosis in the Presence of Embedded Memories", VLSI Design, vol. 12, Article ID 032515, 14 pages, 2001. https://doi.org/10.1155/2001/32515

BIST-Based Fault Diagnosis in the Presence of Embedded Memories

Received15 Aug 1999
Revised11 Sep 2000


An efficient method is described for using fault simulation as a solution to the diagnostic problem created by the presence of embedded memories in BIST designs. The simulation is event-table-driven. Special techniques are described to cope with the faults in the Prelogic, Postlogic, and the logic embedding the memory control or address inputs. It is presumed that the memory itself has been previously tested, using automatic test pattern generation (ATPG) techniques via the correspondence inputs, and has been found to be fault-free.

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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