Table of Contents
VLSI Design
Volume 12, Issue 3, Pages 333-348

CADRE: A Low-power, Low-EMI DSP Architecture for Digital Mobile Phones

AMULET Group, Department of Computer Science, University of Manchester, Oxford Road, Manchester M13 9PL, United Kingdom

Received 20 June 2000; Revised 3 August 2000

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [3 citations]

The following is the list of published articles that have cited the current article.

  • M. Lewis, and L. Brackenbury, “Exploiting typical DSP data access patterns and asynchrony for a low power multiported register bank,” Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001, pp. 4–14, . View at Publisher · View at Google Scholar
  • M. Sokolović, M. Zwolinski, and V. Litovski, “New concepts of worst-case delay evaluation in asynchronous VLSI SoC,” "2008 26th International Conference on Microelectronics, Proceedings, MIEL 2008", pp. 377–386, 2008. View at Publisher · View at Google Scholar
  • Miljana Sokolovic, Vanco Litovski, and Mark Zwolinski, “New concepts of worst-case delay and yield estimation in asynchronous VLSI circuits,” Microelectronics Reliability, vol. 49, no. 2, pp. 186–198, 2009. View at Publisher · View at Google Scholar