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VLSI Design
Volume 12, Issue 3, Pages 431-448
http://dx.doi.org/10.1155/2001/67893

Low Power Built-In Self-Test Schemes for Array and Booth Multipliers

Department of Computer Engineering and Informatics, University of Patras, Patras 26 500, Greece

Received 3 February 2000

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

D. Bakalist, X. Kavousianos, H. T. Vergos, D. Nikolos, and G. Ph. Alexiou, “Low Power Built-In Self-Test Schemes for Array and Booth Multipliers,” VLSI Design, vol. 12, no. 3, pp. 431-448, 2001. https://doi.org/10.1155/2001/67893.