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VLSI Design
Volume 12 (2001), Issue 4, Pages 475-486

Efficient Test Application for Core-Based Systems Using Twisted-Ring Counters

1Department of Electrical and Computer Engineering, Duke University, 130 Hudson Hall, Box 90291, Durham 27708, NC, USA
2Delphi Delco Electronics Systems, IC Design Center, 2705 Goyer Road, P.O. Box 9005, Mail Station D18, Kokomo 46904-9005, IN, USA

Received 15 August 1999; Revised 11 September 2000

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


We present novel test set encoding and pattern decompression methods for core-based systems. These are based on the use of twisted-ring counters and offer a number of important advantages–significant test compression (over 10X in many cases), less tester memory and reduced testing time, the ability to use a slow tester without compromising test quality or testing time, and no performance degradation for the core under test. Surprisingly, the encoded test sets obtained from partially-specified test sets (test cubes) are often smaller than the compacted test sets generated by automatic test pattern generation programs. Moreover, a large number of patterns are applied test-per-clock to cores, thereby increasing the likelihood of detecting non-modeled faults. Experimental results for the ISCAS benchmark circuits demonstrate that the proposed test architecture offers an attractive solution to the problem of achieving high test quality and low testing time with relatively slower, less expensive testers.