VLSI Design

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Volume 12 |Article ID 083474 | https://doi.org/10.1155/2001/83474

P. K. Lala, A. Walker, "A Fine Grain Configurable Logic Block for Self-checking FPGAs", VLSI Design, vol. 12, Article ID 083474, 10 pages, 2001. https://doi.org/10.1155/2001/83474

A Fine Grain Configurable Logic Block for Self-checking FPGAs

Received15 Aug 1999
Revised11 Sep 2000

Abstract

This paper proposes a logic cell that can be used as a building block for Self-checking FPGAs. The proposed logic cell consists of two 2-to-1 multiplexers, three 4-to-1 multiplexers and a D flip-flop. The cell has been designed using Differential Cascode Voltage Switch Logic. It is self-checking for all single transistor stuck-on and stuck-off faults as well as stuck-at faults at the inputs of each multiplexers and the D flip-flop. The multiplexers and the D flip-flop provide either correct (complementary) output in the absence of above-mentioned faults; otherwise the outputs are identical.

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


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