VLSI Design

VLSI Design / 2001 / Article
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VLSI Testing

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Volume 12 |Article ID 087048 | https://doi.org/10.1155/2001/87048

Shih-Chieh Chang, Kwen-Yo Chen, Ching-Hwa Cheng, Wen-Ben Jone, Sunil R. Das, "Random Pattern Testability Enhancement by Circuit Rewiring", VLSI Design, vol. 12, Article ID 087048, 13 pages, 2001. https://doi.org/10.1155/2001/87048

Random Pattern Testability Enhancement by Circuit Rewiring

Received15 Aug 1999
Revised11 Sep 2000

Abstract

Generally, there exist random-pattern resistant faults that result in the poor fault coverage in Build-In Self-Testing (BIST) scheme. In this paper, we propose a method to enhance the random pattern testability by a circuit restructuring technique, called circuit rewiring. The basic idea of rewiring is to replace a wire by another wire with the circuit functionality remaining unchanged. For two types of rewiring, fanin rewiring and fanout rewiring, we first analyze the testability change for each type of wire replacement. Based on the analysis, an efficient algorithm is given to enhance circuit testability. For a poor observability node, we try to increase its observability by adding an additional fanout to the node and removing an alternative wire whose source node has relatively good observability. The technique does not introduce any hardware overhead and performance degradation since a wire addition is followed immediately by another wire removal. Thus, it is basically cost-free when compared to other testability enhancement techniques.

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


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