Table of Contents
VLSI Design
Volume 12, Issue 4, Pages 537-549

Random Pattern Testability Enhancement by Circuit Rewiring

1Department of Computer Science and Information Engineering, National Chung Cheng University, Chiayi 621, Taiwan
2School of Information Technology and Engineering, University of Ottawa, Ottawa, Ontario KIN 6N5, Canada
3Department of Electrical and Computer Engineering and Computer Science, University of Cincinnati, Cincinnati, OH 45221, USA

Received 15 August 1999; Revised 11 September 2000

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Shih-Chieh Chang, Kwen-Yo Chen, Ching-Hwa Cheng, Wen-Ben Jone, and Sunil R. Das, “Random Pattern Testability Enhancement by Circuit Rewiring,” VLSI Design, vol. 12, no. 4, pp. 537-549, 2001.