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VLSI Design
Volume 13, Issue 1-4, Pages 111-115
http://dx.doi.org/10.1155/2001/90787

Impact of Scaling on CMOS Chip Failure Rate, and Design Rules for Hot Carrier Reliability

1Beckman Institute, Department of Electrical and Comuter Engineering and Department of Physics, University of Illinois, Urbana, IL 61801, USA
2Department of Electrical Engineering, University of Texas, Austin, TX 78712-1100, USA

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Amr Haggag, William McMahon, Karl Hess, Björn Fischer, and Leonard F. Register, “Impact of Scaling on CMOS Chip Failure Rate, and Design Rules for Hot Carrier Reliability,” VLSI Design, vol. 13, no. 1-4, pp. 111-115, 2001. https://doi.org/10.1155/2001/90787.