Table of Contents
VLSI Design
Volume 12, Issue 4, Pages 563-578

BIST Analysis of an Embedded Memory Associated Logic

ECE Dept., New Jersey Institute of Technology, University Heights, Newark 07102-1982, New Jersey, USA

Received 15 August 1999; Revised 11 September 2000

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Jacob Savir, “BIST Analysis of an Embedded Memory Associated Logic,” VLSI Design, vol. 12, no. 4, pp. 563-578, 2001.