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VLSI Design
Volume 12, Issue 3, Pages 377-390
http://dx.doi.org/10.1155/2001/97598

A Regularly Structured Parallel Multiplier with Low-power Non-binary-logic Counter Circuits

Department of Computer Science, SUNY at Geneseo, Geneseo 14454, NY, USA

Received 20 June 2000; Revised 3 August 2000

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Rong Lin, “A Regularly Structured Parallel Multiplier with Low-power Non-binary-logic Counter Circuits,” VLSI Design, vol. 12, no. 3, pp. 377-390, 2001. https://doi.org/10.1155/2001/97598.