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VLSI Design
Volume 2010 (2010), Article ID 251210, 25 pages
http://dx.doi.org/10.1155/2010/251210
Research Article

Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments

1Department of Electrical and Computer Engineering, George Washington University, 20101 Academic Way, Ashburn, VA 20147-2604, USA
2Department of Electrical Engineering and Computer Science, University of Tennessee, 414 Ferris Hall, Knoxville, TN 37996-2100, USA

Received 7 June 2009; Accepted 2 November 2009

Academic Editor: Ethan Farquhar

Copyright © 2010 Saumil G. Merchant and Gregory D. Peterson. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [4 citations]

The following is the list of published articles that have cited the current article.

  • N. Izeboudjen, A. Bouridane, A. Farah, and H. Bessalah, “Application of design reuse to artificial neural networks: case study of the back propagation algorithm,” Neural Computing and Applications, vol. 21, no. 7, pp. 1531–1544, 2011. View at Publisher · View at Google Scholar
  • N. Izeboudjen, C. Larbes, and A. Farah, “A new classification approach for neural networks hardware: from standards chips to embedded systems on chip,” Artificial Intelligence Review, vol. 41, no. 4, pp. 491–534, 2012. View at Publisher · View at Google Scholar
  • Vishnu P. Nambiar, Mohamed Khalil-Hani, M.N. Marsono, and C.W. Sia, “Optimization of Structure and System Latency in Evolvable Block-Based Neural Networks using Genetic Algorithm,” Neurocomputing, 2014. View at Publisher · View at Google Scholar
  • Vishnu P. Nambiar, Mohamed Khalil-Hani, Riadh Sahnoun, and M.N. Marsono, “Hardware Implementation of Evolvable Block-Based Neural Networks Utilizing a Cost Efficient Sigmoid-Like Activation Function,” Neurocomputing, 2014. View at Publisher · View at Google Scholar