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VLSI Design
Volume 2010 (2010), Article ID 451809, 9 pages
Research Article

Post-CTS Delay Insertion

Department of Electrical and Computer Engineering, Drexel University, Philadelphia, PA 19104, USA

Received 29 May 2009; Revised 23 October 2009; Accepted 18 November 2009

Academic Editor: Gregory D. Peterson

Copyright © 2010 Jianchao Lu and Baris Taskin. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A post-clock-tree-synthesis (post-CTS) optimization method is proposed that suggests delay insertion at the leaves of the clock tree in order to implement a limited version of clock skew scheduling. Delay insertion is limited on each clock tree branch simultaneous with a global monitoring of the total amount of delay insertion. The delay insertion for nonzero clock skew operation is performed only at the clock sinks in order to preserve the structure and the optimizations implemented in the clock tree synthesis stage. The methodology is implemented as a linear programming model amenable to two design objectives: fixing timing violations or optimizing the clock period. Experimental results show that the clock networks of the largest ISCAS'89 circuits can be corrected post-CTS to resolve the timing conflicts in approximately 90% of the circuits with minimal delay insertion (0.159   ×   clock period per clock path on average). It is also shown that the majority of the clock period improvement achievable through unrestricted clock skew scheduling are obtained through very limited insertion ( 43% average improvement through 10% of max insertion).