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VLSI Design
Volume 2010 (2010), Article ID 460312, 9 pages
http://dx.doi.org/10.1155/2010/460312
Research Article

Error Immune Logic for Low-Power Probabilistic Computing

School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332, USA

Received 27 May 2009; Accepted 19 November 2009

Academic Editor: Gregory D. Peterson

Copyright © 2010 Bo Marr et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [2 citations]

The following is the list of published articles that have cited the current article.

  • Walid Ibrahim, and Valeriu Beiu, “Using Bayesian networks to accurately calculate the reliability of complementary metal oxide semiconductor gates,” IEEE Transactions on Reliability, vol. 60, no. 3, pp. 538–549, 2011. View at Publisher ยท View at Google Scholar
  • Marco Donato, R. Iris Bahar, William R. Patterson, and Alexander Zaslavsky, “A Sub-Threshold Noise Transient Simulator Based on Integrated Random Telegraph and Thermal Noise Modeling,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 3, pp. 643–656, 2018. View at Publisher ยท View at Google Scholar