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VLSI Design
Volume 2010 (2010), Article ID 512312, 14 pages
Research Article

FPGA-Based Software Implementation of Series Harmonic Compensation for Single Phase Inverters

1Department of Electrical Engineering, Indian Institute of Information Technology Design & Manufacturing Kancheepuram, IIT Madras campus, Chennai-600036, India
2Department of Electrical Engineering, Indian Institute of Technology Madras, Chennai-600036, India

Received 10 June 2009; Accepted 20 October 2009

Academic Editor: Gregory D. Peterson

Copyright © 2010 K. Selvajyothi and P. A. Janakiraman. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper presents a single chip FPGA (Altera Cyclone II) controlled single phase inverter, programmed for the reduction of harmonics in the output voltage. Separate composite digital observers have been designed for extracting the fundamental and harmonic components of the voltage and the highly distorted current signals, particularly when the inverter supplies nonlinear loads. These observers have been embedded into the FPGA along with the controllers and I/O interfaces. The multiple observers yield very pure in-phase and quadrature voltage signals for use in the outer loop and similar signals for stabilizing the inner current loop. The Inverter could be modeled as a feed back control system with the fundamental component of the voltage as the desired output while the voltage harmonics take the role of noise creeping into the output. To obtain a very low total harmonic distortion in the voltage waveform, the well-known control strategy of using a very large feed back around the noise signal has been employed.