Research Article  Open Access
A HighSpeed and LowEnergyConsumption Processor for SVDMIMOOFDM Systems
Abstract
A processor design for singular value decomposition (SVD) and compression/decompression of feedback matrices, which are mandatory operations for SVD multipleinput multipleoutput orthogonal frequencydivision multiplexing (MIMOOFDM) systems, is proposed and evaluated. SVDMIMO is a transmission method for suppressing multistream interference and improving communication quality by beamforming. An application specific instructionset processor (ASIP) architecture is adopted to achieve flexibility in terms of operations and matrix size. The proposed processor realizes a highspeed/lowpower design and realtime processing by the parallelization of floatingpoint units (FPUs) and arithmetic instructions specialized in complex matrix operations.
1. Introduction
In recent years, multipleinput multipleoutput orthogonal frequencydivision multiplexing (MIMOOFDM) has been attracting attention as a scheme for achieving highspeed and largecapacity wireless communications. MIMOOFDM has been adopted for the current wireless LAN standard, IEEE 802.11n [1], and for the nextgeneration wireless LAN standard, IEEE 802.11ac [2].
It is possible to increase the communication capacity in MIMO systems by increasing the number of transmit and receive antennas; however, communication quality is degraded by the consequent multistream interference. As a solution to this degradation problem, singular value decomposition (SVD) MIMO systems are used. In the case of SVDMIMO systems, it is possible to suppress multistream interference and to improve communication quality with beamforming using SVD [3]. The implementation of SVD by applying custom hardware processors has been reported in recent studies [4–7]. These processors provide highspeed calculation and enough accuracy for 4 4 SVDMIMO systems. However, SVDMIMO systems require not only SVD calculation but also other operations such as compression and decompression of feedback matrices [8] and should support a variety of matrix sizes depending on their configuration. Additionally, applying dedicated hardware only to SVD calculation is not superior in terms of utilization efficiency. Therefore, we have employed an application specific instructionset processor (ASIP) architecture to achieve both flexibility and high processing efficiency. The ASIP implementation of QR decomposition supporting MIMO systems has been presented in [9]. However, it does not support SVDMIMO systems.
This study mainly deals with 4 4 SVDMIMOOFDM systems; in particular, flexible processor supporting SVD of MIMO channel matrices and compression/decompression of feedback matrices was designed. The processor achieves efficient, realtime processing by parallelization of floatingpoint units (FPUs) and arithmetic instructions specialized in complex matrix operations. Since the processor employs an ASIP architecture and a floatingpoint data format, it can deal with other operations and larger matrix sizes (e.g., 8 8) while keeping high calculation accuracy. The improvement compared to our previous work [10] has been achieved by simplifying FPUs and optimizing calculation bit length. Additionally, a “packetskip” method for reducing energy consumption and improving communication throughput is proposed and evaluated.
This paper is organized as follows. The theory of SVDMIMO systems is explained in Section 2, and the algorithm of SVD and matrix compression/decompression is described in Section 3. Section 4 explains the structure of the proposed processor. Section 5 presents the evaluated performance of the designed circuit. The packetskip method is explained and evaluated in Section 6. Section 7 presents the conclusions drawn from this study.
2. SVDMIMO System
In an MIMO system with transmit antennas and receive antennas, a transmission signal, goes through a propagation, . A received signal, , is expressed as where is white Gaussian noise. A block diagram of an SVDMIMOOFDM system is illustrated in Figure 1. An SVDMIMO system assumes that channelstate information (CSI) is known in a transmitter and a receiver. By SVD, the channel matrix, , is decomposed into a diagonal matrix, , and two unitary matrices, and , as By beamforming using a transmitweight matrix, , the received signal is expressed as In addition, by applying a receiveweight matrix, , the received signal is finally expressed as where is a diagonal matrix having singular values of in the diagonal elements. The receiver can therefore receive the signal without multistream interference.
To investigate the effect of SVDMIMO on improving transmission performance, bit error rates (BERs) of spacedivision multiplexing (SDM) MIMO without beamforming and of SVDMIMO are compared by a baseband simulation. A 4 4 MIMOOFDM system was used for this BER comparison. The simulation parameters are listed in Table 1 and the characteristics of SDMMIMO and SVDMIMO are compared in Figure 2. The figure shows that the beamforming by SVDMIMO gains about 3 to 5 dB in carrier to noise ratio (CNR) for BER of .

3. Algorithm
3.1. Singular Value Decomposition
SVD is a method of matrix decomposition in linear algebra. By SVD, channel matrix is decomposed as where is an diagonal matrix, and its diagonal elements are called singular values: and are unitary matrices. The columns of and are, respectively, called “left singular vectors” and “right singular vectors.” The SVD of is calculated in the following three steps.(a)Bidiagonalization : calculate upper bidiagonal matrix by bidiagonalization using a Householder transformation.(b)SVD of bidiagonal matrix : execute eigenvalue decomposition of by a QR algorithm and calculate from , .(c)Inverse transform , : calculate unitary matrices and from and and and , respectively, in steps (a) and (b).
3.1.1. Eigenvalue Decomposition by QR Algorithm
QR is an algorithm for calculating the eigenvalues of a matrix. It executes the QR decomposition iteratively. The QR decomposition decomposes a matrix into a product of a unitary matrix, , and an upper triangle matrix, . QR is executed by repeating the following operations: Since this iterative process is a similarity transformation, the eigenvalues of are all equal. When is a Hermitian matrix, converges to a diagonal matrix, and the eigenvalues are obtained. When is a tridiagonal matrix, is also a tridiagonal matrix. In the case of SVD calculation, matrix is a tridiagonal Hermitian matrix. therefore converges to diagonal matrix : The Givens rotation algorithm (which is the linear transformation by the matrix for the QR decomposition) is adopted, and the number of iterations in the QR algorithm is set to 10.
3.2. FeedbackMatrix Compression
A SVDMIMO system has a drawback of which throughput is decreased by “matrix feedback.” To address this drawback, compression of the feedback matrix is effective. Accordingly, the compression method of a unitary matrix that is adopted in the IEEE 802.11n standard [1] is used. This method transforms a unitary matrix into angles by real transformation and the Givens rotation. It assumes that the th row of an unitary matrix, , is transformed into real numbers in the preprocessing. For , , a matrix, , which transforms the th column into real numbers is generated by where is an argument of at the th row and th column. By multiplying by , the th column of becomes real numbers. As a result, nondiagonal elements at the th column in become zero according to the Givens rotation. The Givens rotation matrix, , and its elements are generated by By multiplying and the Givens rotation matrices , nondiagonal elements at the th column in become zero. Since is a unitary matrix, nondiagonal elements at the th row in also become zero, and the element at the th row and the th column in becomes one, which is expressed as By repeating these processes for , matrix is finally transformed into an identity matrix, . Here, applying (9) and (10) generates the real transformation matrix, , and the Givens rotation matrix, , from phases and , respectively. Moreover, applying (13) makes it possible to compute from as follows: Since the receiver feeds back only phases and , the feedback data is transformed from complex elements into positive real phases. Table 2 compares the feedback data sizes between noncompressed data and compressed data. Each quantization bit rate is determined by a baseband simulation to avoid degradation of communication performance. In the case of noncompressed data, both the real part and the imaginary part are quantized in seven bits. On the other hand, in the case of compressed data, and are quantized in seven bits and five bits, respectively.

4. Processor Structure
An application specific instructionset processor (ASIP) architecture has been employed for the processor architecture, and efficient processing and flexibility were achieved by preparing arithmetic instructions specialized in complex matrix operations.
4.1. Circuit Structure
The circuit structure of the proposed processor is illustrated in Figure 3. Data and instructions are stored to each memory unit, and the processing unit executes instructions in order. The floatingpoint data format supports complex values, and each part of a complex value consists of a 1bit sign part, a bits exponent part, and bits mantissa part, whose format is shown in Figure 4. Basically, each bit length is based on the IEEE 754 standard . Data memories and processing units are arrayed by the number of parallel processing. Two types of data transfers, which are shown in Figure 5, are supported. A singledata transfer sends data to the processing unit one by one. On the other hand, a blockdata transfer sends data blocks containing multiple entries to the processing unit. The structure of the processing unit, which consists of nine floatingpoint units (FPUs) and dedicated circuits for division and squareroot operation [11], is shown in Figure 6. “FPU1” to “FPU4” are used for multiplication, and “FPU5” to “FPU9” are used for addition and subtraction; in particular, “FPU9” is used for only CORDIC operations, which are described in Section 4.4. A variety of instructions can be executed by changing the data paths in the processing unit.
(a) Single data transfer
(b) Block data transfer
4.2. Instruction Format
The instruction format consists of memory addresses of input data , , output data , and operation type, whose format is shown in Figure 7. The bit lengths are given as bits and bits, where is the number of data memory words, and is the number of instructions. Table 3 lists the instructions supported by the proposed processor.

4.3. Complex Operation
The proposed processor achieves efficient processing in complex matrix operations by adopting specialized instructions and an operationunit structure. For instance, the complex multiplication of is executed in seven cycles using “FPU1” to “FPU4,” “FPU5,” and “FPU6” for multiplication, subtraction and addition, respectively, as shown in Figure 8. Moreover, the accumulative complex multiplication is executed in nine cycles using the registers of “Accr”, “Acci,” and “FPU7,” and “FPU8” as shown in Figure 9.
4.4. CORDIC Method
The proposed processor executes approximate calculation by the CORDIC (coordinate rotation digital computer) method for calculating trigonometric functions, which is necessary for the matrix compression and decompression. The recurrence formulas used in the CORDIC method are expressed by By setting the initial values to and selecting −1 or 1 for so that approaches zero, it is possible to calculate cosine and sine values as On the other hand, setting the initial values to and selecting −1 or 1 for so that approaches zero makes it possible to calculate an arctangent value as To execute the CORDIC operations in the processing unit, five FPUs are used, as shown in Figure 10, where the signs of input data , at “FPU1,” “FPU2,” and “FPU9” are reversed depending on the condition. The values of are loaded from the data memory unit. And the number of iterations used with the CORDIC method is set to 10.
4.5. Division and SquareRoot Operation
In the case that only “FPU1” to “FPU8” are used, the division and squareroot operations are executed by approximate calculation using the NewtonRaphson method. However, they require 115 cycles and 1430 cycles, respectively. The implementation of dedicated circuits for division and squareroot operation is effective for hardware acceleration. Division and squareroot floatingpoint units [11] were therefore adopted. Since those units can execute division and squareroot operation in 11 cycles, calculation time can be significantly reduced.
4.6. BitLength Optimization
Since required precision depends on systems, circuit area and power consumption can be reduced by decreasing bit length. To optimize the mantissa bit length of the proposed processor for SVD and matrix compression/decompression, BER characteristics for several bit lengths were evaluated by simulation. The simulation parameters are the same as listed in Table 1, and the characteristics evaluation is shown in Figure 11. From this figure, the optimal mantissa bit length is taken as 12 bits.
5. Performance Evaluation
5.1. Circuit Design
The proposed processor was designed by using Verilog hardware description language and synthesized in the controller and the processing units by using a 90 nm CMOS standard cell library. The clock frequency was set to 400 MHz (2.5 ns in a clock period), and the supply voltage was set to 1.0 V.
5.2. Circuit Performance
The circuit performance was evaluated in cases with or without division and squareroot units. The results are listed in Tables 4 and 5, respectively. The calculation time for all channel matrices of 108 data subcarriers was measured. The number of entries in the block data transfer was set to 18 to minimize energy consumption. According to these results, the implementation of the division and squareroot units increases circuit area twofold and power consumption by half. However, since the calculation time can be reduced to , energy consumption can be reduced to . This comparison shows that the implementation of division and squareroot units is effective.


5.3. BitLength Limitation
In the previous section, circuit performance without bit length limitation was evaluated. In contrast, in this section, circuit performance with bit length limitation is evaluated (see Table 6). In this evaluation, division and squareroot units were implemented and the bitlength limitation is applied in multipliers only, which account for large portion of the operation. This result shows that the bitlength limitation can reduce circuit area, power consumption, and energy consumption by about 10%, 20%, and 20%, respectively.

5.4. Processing Time
A timing chart of the SVDMIMOOFDM system is shown in Figure 12. It is assumed that the update and feedback of CSI are executed at every packet. The calculation of SVD and the matrix compression must be completed between receiving the preamble of the data packet and sending the feedbackmatrix data. When the number of OFDM data symbols, , is 50, the acceptable calculation time is 252 s. When the proposed processor arrays six processing units by parallel processing, it takes 193 s for SVD and matrix compression. Since the calculation time is less than the acceptable calculation time, the processor realizes realtime processing.
5.5. Comparison with Related Works
The proposed processor is compared here with our previous work [10] and other related works [4–6] in Table 7. Compared with our previous work, the proposed processor has improved throughput by almost four times, even though it also performs matrix compression. This improvement was achieved by simplifying FPUs and imposing the bitlength limitation. In consideration of SVD operation only, the performance of the proposed processor is not superior to that of either [5] or [6]. However, it can realize sufficient realtime processing and support not only SVD but also matrix compression and decompression (MCD). It therefore achieves faster communication throughput than the other processors. Furthermore, since the proposed processor employs an ASIP architecture and floatingpoint data format, it can deal with other operations and larger matrix sizes while keeping high calculation accuracy. Given these advantage features, it is concluded that the proposed processor can realize an SVDMIMOOFDM system more effectively than the other processors.

6. PacketSkip Method
As explained in the previous sections, it was assumed that the system feeds back the weight matrix at every packet. However, if the channel state is changed gradually, it is possible to skip the SVD calculation and the feedback of the weight matrix and to apply the previous weight matrix without degradation of BER. On the basis of this idea, energy consumption can be reduced and communication throughput can be increased by skipping the SVD calculation and the weightmatrix feedback.
6.1. Simulation
To determine the optimal skip number, BER characteristics for several numbers of packet skips were evaluated by simulation. The simulation assumed a communication environment with the 10 Hz Doppler frequency. The simulation parameters are listed in Table 8, and the BER evaluation result is shown in Figure 13. The delay in this figure means the numbers of packet skips. The packet skip is applied from the packet at which the SVD calculation process starts to the packet to which weight matrices are applied. According to this figure, a delay of less than 5 packets is acceptable under this communication environment. Additionally, BER characteristics in a communication environment with the 1 Hz Doppler frequency were evaluated. The simulation parameters are listed in Table 9, and the BER evaluation result is shown in Figure 14. According to this figure, a delay within 30 to 40 packets is acceptable under this communication environment.


6.2. Skip Method
For packet skipping, two methods (illustrated schematically in Figure 15) are proposed. As for the first method, that is, method A, SVD calculation is executed over one packet and the weight matrices are applied to the next packets. The delay produced by method A is packets. On the other hand, as for the second method, that is, method B, SVD is calculated over packets, and the weight matrices are applied to the packets after the SVD calculation. The delay produced by method B is packets. In the case of method A, total energy consumption is reduced by . In the case of method B, the power consumption can be reduced since the calculation time of SVD is longer than that of the nonskip system or method A.
6.3. Performance Evaluation
Circuit performance and communication throughput when these skip methods were applied was evaluated. In the evaluation, it was assumed that the delay is 5 packets for a communication environment with the 10 Hz Doppler frequency. Accordingly, and 3 for methods A and B, respectively. The results of the performance evaluation are listed in Table 10. In the evaluation, communication throughput was calculated under the assumption that signals are transmitted by 4 4 SVDMIMO (64QAM, , and 50 symbols) and the feedbacks are transmitted by 4 4 SDMMIMO (16QAM, ). According to these performance results, method A is the most effective in terms of energy consumption and communication throughput.

7. Concluding Remarks
A processor design for SVDMIMOOFDM systems was proposed. The proposed processor employs an ASIP architecture and achieves both flexibility and high throughput by parallelization of FPUs and arithmetic instructions that are specialized in complex matrix operations. In addition, two types of packetskip method for reducing energy consumption and increasing communication throughput were proposed. In future work, we will deal with largerscale SVDMIMOOFDM systems (e.g., 8 8 SVDMIMO).
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Copyright
Copyright © 2013 Hiroki Iwaizumi et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.