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VLSI Design
Volume 2014, Article ID 380362, 5 pages
http://dx.doi.org/10.1155/2014/380362
Research Article

Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits

Shikha Panwar, Mayuresh Piske, and Aatreya Vivek Madgula

School of Electronics Engineering (SENSE), VIT University, Vandalur-Kelambakkam Road, Chennai 600127, India

Received 2 May 2014; Accepted 27 June 2014; Published 15 July 2014

Academic Editor: Yu-Cheng Fan

Copyright © 2014 Shikha Panwar et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Shikha Panwar, Mayuresh Piske, and Aatreya Vivek Madgula, “Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits,” VLSI Design, vol. 2014, Article ID 380362, 5 pages, 2014. https://doi.org/10.1155/2014/380362.