Table of Contents
VLSI Design
Volume 2014, Article ID 529392, 12 pages
Review Article

Gate-Level Circuit Reliability Analysis: A Survey

Department of Electrical and Computer Engineering, University of Windsor, Windsor, ON, Canada N9B 3P4

Received 25 April 2014; Accepted 7 June 2014; Published 10 July 2014

Academic Editor: Yu-Cheng Fan

Copyright © 2014 Ran Xiao and Chunhong Chen. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [4 citations]

The following is the list of published articles that have cited the current article.

  • P. Balasubramanian, and R. T. Naayagi, “Mathematical estimation of logical masking capability of majority/minority gates used in nanoelectronic circuits,” 2017 International Conference on Circuits, System and Simulation (ICCSS), pp. 18–23, . View at Publisher · View at Google Scholar
  • Jinchen Cai, and Chunhong Chen, “Circuit Reliability Analysis Using Signal Reliability Correlations,” 2017 IEEE International Conference on Software Quality, Reliability and Security Companion (QRS-C), pp. 171–176, . View at Publisher · View at Google Scholar
  • Jie Xiao, William Lee, Jianhui Jiang, and Xuhua Yang, “Circuit reliability estimation based on an iterative PTM model with hybrid coding,” Microelectronics Journal, vol. 52, pp. 117–123, 2016. View at Publisher · View at Google Scholar
  • Xingjian Xu, Tian Ban, and Yuehua Li, “SPLM: A Flexible and Accurate Reliability Assessment Model for Logic Circuits,” Journal of Circuits, Systems and Computers, 2018. View at Publisher · View at Google Scholar