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Mathematical Problems in Engineering
Volume 2010 (2010), Article ID 185398, 21 pages
http://dx.doi.org/10.1155/2010/185398
Research Article

An Efficient VLSI Linear Array for DCT/IDCT Using Subband Decomposition Algorithm

1Department of Microelectronics Engineering, Chung Hua University, Hsinchu City 300-12, Taiwan
2Department of Computer Science and Information Engineering, National United University, Miaoli 360-03, Taiwan

Received 30 January 2010; Accepted 22 March 2010

Academic Editor: Ming Li

Copyright © 2010 Tze-Yun Sung et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Discrete Cosine transform (DCT) and inverse DCT (IDCT) have been widely used in many image processing systems and real-time computation of nonlinear time series. In this paper, a novel lineararray of DCT and IDCT is derived from the data flow of subband decompositions representing the factorized coefficient matrices in the matrix formulation of the recursive algorithm. For increasing the throughput as well as decreasing the hardware cost, the input and output data are reordered. The proposed 8-point DCT/IDCT processor with four multipliers, simple adders, and less registers and ROM storing the immediate results and coefficients, respectively, has been implemented on FPGA (field programmable gate array) and SoC (system on chip). The linear-array DCT/IDCT processor with the computation complexity and hardware complexity is fully pipelined and scalable for variable-length DCT/IDCT computations.

1. Introduction

With rapid growth of modern communication applications and computer technologies, image compression and real-time computation of nonlinear time series continues to be in great demand. Discrete Cosine transform (DCT) is one of the major operations in various image/video compression standards [1] and nonlinear time series applications [28]. Though fast Fourier transform (FFT) can be used to implement DCT, it requires complex-valued computations; and moreover, N-point DCT by FFT contains stages. The conventional DCT architectures using distributed arithmetic involve complex hardware with a great number of registers [919]. Other commonly used DCT architectures with matrix formulation and distributed memory [2027] are however not suited for VLSI implementation because the hardware complex is proportional to the length of DCT, which leads to the scalability problem of variable-length DCT computations. In this paper, we propose the novel linear-array architecture for scalable DCT/IDCT implementation.

The remainder of this paper proceeds as follows. In Section 2, we propose the fast DCT/IDCT computation based on subband decomposition algorithm. In Section 3, the reconfigurable FPGA-based and programmable SoC implementations with low hardware cost are proposed for the fast DCT/IDCT computation. The performance comparison with conclusions can be found in Section 4.

2. Proposed Fast DCT/IDCT Computation

For an N-point signal, , the discrete cosine transform (DCT) [28] is defined as where , and for . Let and denote the low-frequency and high-frequency subband signals of , respectively, which are defined as where . The original signal can be obtained from and as follows: As one can see, the DCT of can be rewritten as where and are the subband DCT and DST (discrete sine transform) of , respectively.

2.1. Fast DCT Computation Based on Subband Decomposition Algorithm

Without loss of generality, the 8-point fast DCT based on subband decomposition algorithm is proposed for the widely used JPEG and MPEG-1/2 standards, which can be easily extended to variable-length DCT computations. The vector form of 8-point DCT can be written as where , , , and and denote the matrices of subband DCT and subband DST, respectively, which can form orthonormal bases for the two orthogonal subspaces of . Notice that, due to the orthogonality between and , and can be obtained from as follows: where , and .

The proposed fast DCT algorithm is a subband decomposition-based multistage algorithm. Specifically, let where . And let where . Based on subband decompositions using (2.2), (2.7), and (2.8), data flow of computing the 2-point subband DCT: and subband DST: for the 8-point DCT is shown in Figure 1. As one can see, data flow of computing and can be obtained in a similar way, and therefore is not shown in Figure 1. All of the 2-point subband DCTs and DSTs are given by Thus, we have where is the original signal, and

185398.fig.001
Figure 1: Data flow of computing the 2-point subband DCT: and subband DST: (for the 8-point DCT of the input signal: ) based on subband decomposition.

Similarly, we have the following: Figure 2 depicts the relationship between and , which can be obtained by the following: According to (2.24)–(2.27), we have Finally, the proposed 8-point DCT computation based on subband decomposition is as follows: where Figure 8 shows block diagram of the proposed DCT computation; one of the advantages is that is orthogonal, and all of the submatrices of are orthonormal.

185398.fig.004
Figure 4: Data flow of computing and using 4-point subband DCT and DST.
185398.fig.005
Figure 5: Data flow of computing and based on subband decomposition.
185398.fig.006
Figure 6: Data flow of computing and based on subband decomposition.
185398.fig.007
Figure 7: Data flow of computing using 8-point subband DCT and DST.
185398.fig.008
Figure 8: Block diagram of the proposed (8-point) fast DCT algorithm based on subband decomposition.
2.2. Fast IDCT Computation Based on Subband Decomposition Algorithm

According to (2.29), IDCT can be obtained by where As is orthogonal and all of the submatrices of are orthonormal, the inverse of and can be obtained easily. In addition, it takes only twenty multiplication operations for both DCT and IDCT.

3. VLSI Implementation of an Efficient Linear-Array DCT/IDCT Processor

Based on the proposed approach to fast DCT computation shown in Figure 8, an efficient architecture for implementing the fast DCT/IDCT processor is thus presented in this section. Recall that the DCT of a signal, , can be efficiently obtained by . Let , then we have . Figure 9 shows the matrix-vector multiplication of , in which six CSA(3,2)s (carry-save-adder (3,2)) and one CSA (carry-save-adder) [29, 30] are utilized, and therefore four simple-addition time and one CSA computation time is required to compute each element of . Figures 10 and 11 show the Multiplier array (MA) consisted of four multipliers and the CSA array (CA) consisted of eight CSAs, respectively, which are used to compute the matrix-vector computation of ; thus, only one multiplication time with one CSA computation time is needed to compute each element of , that is, the DCT coefficient. Table 3 depicts data flow of the proposed fast DCT processor with pipelined linear-array architecture [31]. As a result, only five multiplication cycles with five addition cycles are needed to compute 8-point DCT. In general, for N-point DCT, the computation time and hardware complexity of the proposed fast DCT processor are and , respectively.

185398.fig.009
Figure 9: Fast adder (FA) for the matrix-vector multiplication of . (Note: The width of buses is 32-bit.)
185398.fig.0010
Figure 10: Multiplier array (MA) consisted of four multipliers. (Note: The width of buses is 32-bit.)
185398.fig.0011
Figure 11: CSA array (CA) consisted of eight CSAs. (Note: The width of buses is 32-bit.)

Table 4 shows data flow of the proposed fast IDCT algorithm [31], where is the DCT of an 8-point signal ; , and . Figure 12 shows the so-called full CSA(4,2) (FCSA(4,2)) consisted of two CSA(3,2) and one CSA for the computation of [29, 30]. It is noted that the CSA array consisted of eight CSAs shown in Figure 11 can also be used for the computation of . As shown in Table 4, only five multiplication cycles with three addition cycles are needed to compute 8-point IDCT. As one can see, the computation time and hardware complexity of the proposed fast IDCT architecture are the same as that of the proposed fast DCT architecture. In addition, only 16-word RAM/registers and 10-word ROM are required to store the intermediate results and constants, respectively; and the latency time is only 5-multiplication-cycle.

185398.fig.0012
Figure 12: Full CSA(4,2) consisted of two CSA(3,2) and one CSA.

Figure 13 shows system block diagram of the proposed fast DCT/IDCT architecture. The platform for architecture development and verification has been designed as well as implemented in order to evaluate the development cost. Figure 14 depicts block diagram of the platform, in which the 8051 microcontroller reads data from PC via DMA channel and writes the result back to PC by USB 2.0 bus; the Xilinx XC2V6000 FPGA chip implements the proposed DCT processor [32]. The architecture development and verification board shown in Figure 15 are to verify and evaluate the proposed DCT/IDCT architecture. Moreover, the reusable intellectual property (IP) DCT/IDCT core has also been implemented in Matlab for functional simulations. The hardware code written in Verilog is running on a workstation with the ModelSim simulation tool and Xilinx ISE smart compiler. In addition, the FPGA platform shown in Figure 14 is to verify and evaluate the proposed DCT architecture. It is noted that the throughput can be improved by using the proposed architecture while the computation accuracy is the same as that obtained by using the conventional one with the same word length.

185398.fig.0013
Figure 13: System block diagram of the proposed DCT/IDCT architecture (FA: fast-adder-array, MA: Multiplier array, FCSA(4,2): full CSA(4,2), and CA: CSA- array).
185398.fig.0014
Figure 14: Block diagram of the architecture development and verification platform for the proposed DCT/IDCT processor.
185398.fig.0015
Figure 15: The architecture development and verification board.

The SoC is synthesized by the TSMC 0.18  1P6M CMOS cell libraries [33]. The physical circuit is synthesized by the Astro tool. The circuit is evaluated by DRC, LVS, and PVS [34]. Figure 16 shows the cell-based design flow. The layout view of the 8-point DCT/IDCT processor with 32-bit operand is shown in Figure 17. The core areas are obtained by the Synopsys design analyzer. The power consumptions are obtained by the PrimePower. The reported core size of the implemented the proposed processor is and the power dissipation is 102.2 mW at 1.8 V with clock rate of 1 GHz. Thus, the proposed programmable DCT/IDCT architecture is able to improve the power consumption and computation speed significantly. All the control signals are internally generated on-chip. The proposed DCT/IDCT processor provides both high-throughput and low gate count.

185398.fig.0016
Figure 16: Cell-based design flow.
185398.fig.0017
Figure 17: The layout view of the proposed 8-point DCT/IDCT processor with 32-bit operand.

The proposed reconfigurable DCT/IDCT processor used to compute -point DCT/IDCT on FPGA are composed mainly of the 8-point DCT/IDCT core; the computation complexity using a single 8-point DCT/IDCT core is O(5N/8) for extending N-point DCT/IDCT computation. Note that the transform matrices used for the proposed linear array with 8-point DCT core can be extended to a variety of different sizes. Thus, the proposed architecture is highly scalable.

The linear-array architecture with use of hardware resources has been proposed for trade offs of performance, chip area and power consumption. As a result, it has the advantage of balancing the need for power saving with computation speed.

4. Conclusion

By taking advantage of subband decomposition, a high-efficiency architecture with pipelined structures is proposed for fast DCT/IDCT computation. Specifically, the proposed DCT/IDCT architecture not only improves throughput by more than two times that of the conventional architectures [911, 1519], but also saves memory space significantly [1, 922]. Table 1 shows comparisons between the proposed architecture and the conventional architectures [1, 914] (with dual memory banks), and [1519]. Table 2 shows comparisons with other commonly used architectures [1, 1214, 2024]. For DCT, the algorithm proposed by Feig requires 54 multiplications and 462 additions [27]; the proposed method requires 25 multiplications and 100 additions. Thus, the performance of this work is superior to that of the Feig algorithm. In addition, the proposed fast DCT/IDCT architecture is highly regular, scalable, and flexible. The DCT/IDCT processor designed by using the portable and reusable Verilog is a reusable IP, which can be implemented in various processes; combined with efficient use of hardware resources for tradeoffs of performance, area and power consumption; and therefore is much suited to the JPEG and MPEG-1/2 applications.

tab1
Table 1: Comparisons between the proposed architecture and the conventional architectures.
tab2
Table 2: Comparisons of the proposed architecture and other commonly used architectures.
tab3
Table 3: Data flow of the proposed fast DCT processor with pipelined linear-array architecture (Add.-cycle: addition-cycle and Mul.-cycle: multiplication-cycle).
tab4
Table 4: Data flow of the proposed fast IDCT processor with pipelined linear-array architecture (Add.-cycle: addition-cycle and Mul.-cycle: multiplication-cycle).

Acknowledgments

The National Science Council of Taiwan, Taipei, Taiwan, under Grant NSC98-2221-E-216-037 and the Chung Hua University, Hsinchu, Taiwan, under Grant no. CHU-NSC98-2221-E-216-037 supported this work.

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