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Advances in Materials Science and Engineering
Volume 2013, Article ID 692469, 8 pages
Research Article

Effect of Coercive Voltage and Charge Injection on Performance of a Ferroelectric-Gate Thin-Film Transistor

1Japan Science and Technology Agency, ERATO, Shimoda Nano-Liquid Process Project, 2-13 Asahidai, Nomi, Ishikawa 923-1211, Japan
2Green Devices Research Center, Japan Advanced Institute of Science and Technology (JAIST), 2-13 Asahidai, Nomi, Ishikawa 923-1211, Japan
3Yokkaichi Research Center, JSR Corporation, Yokkaichi 510-8552, Japan
4School of Materials Science, Japan Advanced Institute of Science and Technology, 1-1 Asahidai, Nomi, Ishikawa 923-1211, Japan

Received 11 October 2013; Accepted 27 November 2013

Academic Editor: Tung-Ming Pan

Copyright © 2013 P. T. Tue et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


We adopted a lanthanum oxide capping layer between semiconducting channel and insulator layers for fabrication of a ferroelectric-gate thin-film transistor memory (FGT) which uses solution-processed indium-tin-oxide (ITO) and lead-zirconium-titanate (PZT) film as a channel layer and a gate insulator, respectively. Good transistor characteristics such as a high “on/off” current ratio, high channel mobility, and a large memory window of 108, 15.0 cm2 V−1 s−1, and 3.5 V were obtained, respectively. Further, a correlation between effective coercive voltage, charge injection effect, and FGT’s memory window was investigated. It is found that the charge injection from the channel to the insulator layer, which occurs at a high electric field, dramatically influences the memory window. The memory window’s enhancement can be explained by a dual effect of the capping layer: (1) a reduction of the charge injection and (2) an increase of effective coercive voltage dropped on the insulator.