Cosimulation of Power and Temperature Models at the SystemC/TLM for a Soft-Core Processor

Table 1

Primary parameters of the power models.

	Name	Description
Architectural		Depletion-layer capacitance per unit area
		Thermal voltage
		Gate capacitance
		Gate width
		Gate length
		Electron mobility
		Subthreshold-swing coefficient
		Gate oxide capacitance per unit area
		Threshold voltage
Algorithmic		Voltage
		Frequency
		Temperature
		Activity ratio