Research Article  Open Access
Implementation of Power Efficient Flash AnaloguetoDigital Converter
Abstract
An efficient low power high speed 5bit 5GS/s flash analoguetodigital converter (ADC) is proposed in this paper. The designing of a thermometer code to binary code is one of the exacting issues of low power flash ADC. The embodiment consists of two main blocks, a comparator and a digital encoder. To reduce the metastability and the effect of bubble errors, the thermometer code is converted into the gray code and there after translated to binary code through encoder. The proposed encoder is thus implemented by using differential cascade voltage switch logic (DCVSL) to maintain high speed and low power dissipation. The proposed 5bit flash ADC is designed using Cadence 180 nm CMOS technology with a supply rail voltage typically ±0.85 V. The simulation results include a total power dissipation of 46.69 mW, integral nonlinearity (INL) value of −0.30 LSB and differential nonlinearity (DNL) value of −0.24 LSB, of the flash ADC.
1. Introduction
Flash ADC has a high data conversion speed, low resolution, and large chip area along with large power dissipation and is therefore preferred for providing high sampling rates. Other architectures like successive approximation register, sigma delta, and dual slope offer less data rate and high resolution compared to flash converter [1–4].
The sparkle or bubble error is caused due to the imperfect input settling time or mismatching time of inputs of comparator. If the output of comparator is either a logic “1” or logic “0,” then this condition is known as metastability condition that can be reduced by using Gray code encoder because Gray code encoding allows only 1bit change in the output at a time which may improve metastability.
The typical block diagram of flash ADC is as shown in Figure 1. The blocks of flash ADCs are resistor string, comparator’s block, and thermometer to gray and gray to binary encoder. It plays an important role especially in optical data recording, magnetic read channel applications, digital communication systems, and so forth that require a high data processing rate and optical communication systems [5–10]. Generally, multiGS/s ADCs which have low resolution are used in high speed measurement systems [11]. The flash ADC contains bunch of resistors and comparators for bit ADC. The resistor string provides reference voltage () to comparators. These reference voltages and input signal voltages () are simultaneously activated by the comparators containing comparators [2]. If , then the output of comparator goes high and when , the output of comparator records low. Hence, the output of comparator is known as thermometer code. Flash ADC is designed for 5 bits () and the number of resistors required is , whereas the number of comparators required is . The important role for ADC is performed by analogue blocks. The design constraints of conversion speed are defined especially by the comparators used in the design of flash ADC [8].
ADCs are used in application areas of camera, digital TVs, mobile phones, wireless sensor networks, transmitter and receiver circuits, and the conversion processes of signals for base band applications [12–16].
The thermometer code is a good solution for low resolution and high speed converters; as the error rate increases, the resolution and the speed also increase [15, 16].
The flash ADC requires a more number of comparators to increase resolution. There is an exponential increase in the number of comparators; hence, the circuit requires large chip area, high bandwidth, and more power consumption. Another important area of 5bit flash ADC is in the application of orthogonal frequency division multiplexing ultrawide band systems [17–21]. There has been much work in implementation of low power and high speed encoders for the design of the flash ADC. The ROMbased encoder is simple and straight forward design, as it is slow and cannot suppress bubble errors. Wallace tree based encoder counts the number of bits “1” in the thermometer code. The disadvantages of this encoder are large delay and power consumption [22–24]. In this approach, the thermometer code to Gray code and Gray to binary code encoders is used, where the gray code encoder is efficient in removing metastability condition and in suppressing the bubble errors. The encoder in this paper has the benefits of high encoding speed and low power consumption, as the DCVSL is used to gain high speed. The proposed flash ADC is designed using encoder as shown in Figure 8.
The rest of the paper is endowed with all design steps and simulation results. The concluding section of the proposed flash ADC performance is compared with the similar designs in the references.
2. Design Steps of 5Bit Flash ADC
The proposed flash ADC block diagram is as shown in Figure 2. It consists of comparator block, thermometer to Gray code encoder block, and Gray code to binary code encoder block.
2.1. Comparator Structure
The comparator circuit of the designed flash ADC is as shown in Figure 3 and the transistor aspect ratios are given in Table 1. In this schematic, transistors , are the NMOS input differential pairs driven by tail current NMOS transistor. This differential pair is loaded by PMOS crosscoupled transistors (), which has a positive feedback loop and diodeconnected PMOS transistors (). The purpose of crosscoupled feedback loop is to increase the voltage gain of differential pair () and to load the output resistance. and form a current mirror and its reference current is provided by the transistors () together [9].

The common source PMOS amplifier () amplifies the firststage output of the comparator [21]. The last stage of the comparator is current source inverter circuit (). This inverter achieves higher voltage gain than CMOS inverter [22]. The results of the complete comparator are shown in Figures 4(a), 4(b), and 4(c). The offset voltage and gain band width product of comparator are 17.2 mV and 6.77 GHz.
(a) Transient analysis of comparator
(b) The DC analysis results of the comparator
(c) Gain plot of the comparator
2.2. Design of the Proposed Encoder
The conversion of the thermometer code output of the comparator to binary code is one of the bottlenecks in the high speed flash ADC design [1]. Programmable logic arrayreadonly memory, exclusive OR encoder, or Wallace tree encoder structures are generally used for conversion [23, 24]. The Wallace tree adder technique is effective in removing the bubble errors but it is at the cost of speed reduction and increased power dissipation [25]. The metastability condition occurs due to the time variation between the comparators input and the effect of bubble errors can be reduced by converting the thermometer code to Gray code. The truth table corresponding to 5bit binary to gray code is presented in Table 2. The relationship between thermometer code, Gray code, and binary code is given below [3]: The equations are derived from the following truth Table 2 for this encoder.

2.3. Implementation of the Proposed Encoder
There are different logic styles to implement the design of the thermometer code to Gray and Gray to binary code encoders. To avoid the static power dissipation and to achieve high speed, the implementation of encoder is validated using DCVSL [26]. DCVSL gate has speed advantage over pseudoNMOS logic, there by the parasitic capacitance of the output node of DCVSL logic gets reduced and faster response is achieved. The static power consumption present in static CMOS logic is eliminated in DCVSL [9]. DCVSL is a CMOS circuit technique that has potential advantages over conventional NOR/NAND logic in terms of circuit delay, layout density, logic flexibility, and power dissipation [10].
The design of CMOS logic with DCVSL has many advantages over static CMOS logic approach, and DCVSL has speed advantage over domino logic circuit. This logic style has both noninverting and inverting logic implementation, where domino logic cannot implement inverting logic operational gates. However, these advantages are achieved at the expense of the large area and the complexity associated with dual logic networks including complementary signals [27].
In this paper DCVSL circuit is proposed, which does not require complementary inputs. The proposed DCVSL simplifies the logic tree complexity, reduces dynamic power, and improves the performance of the circuits. The proposed DCVSL is as shown in Figure 5.
To reduce the power consumption and to increase the performance, many clocked versions of DCVSL gates have been introduced. The reduction of parasitic capacitances at the output node provides a faster response and the static power consumption is eliminated [28, 29]. The operation of DCVSL is as follows. During precharge () phase, transistors , are turned ON; the output node is charged to . The input is given to the NMOS logic tree and the logic of operation is implemented using nchannel MOSFET. A diode works as a dynamic current source to limit the amount of charge transferred from one output node. For the implementation of fast errorcorrection logic in memories, this DCVSL logic can be used [10]. The schematic of the Gray code encoder for each bit is designed using proposed circuits shown in Figure 6.
(a) Gray code BIT0 generation circuit
(b) Gray code BIT1 generation circuit
(c) Gray code BIT2 generation circuit
(d) Gray code BIT3 generation circuit
(e) Gray code BIT4 generation circuit
The circuits of Gray code bit0, 1, 2, 3, 4 are shown in Figures 6(a), 6(b), 6(c), 6(d), and 6(e). The logic of these circuits is designed from (1) using the DCVS logic, and a CMOS inverter is used at the output stage of the circuit.
By using the XOR gate, the Gray code will be converted into binary code. The schematic of 2input XOR gate is as shown in Figure 7. The design of complete encoder is as shown in Figure 8. The results of the proposed encoder are presented in Table 3.

3. Simulation Results
The complete design of 5bit 5GS/s flash ADC circuit as shown in Figure 1 is simulated using Cadence and the model parameters of a gpdk 180 nm CMOS process. As resolution increases, the maximum frequency of operation will get decreased. The encoder in Figure 8 is simulated by providing thermometer code as input which is presented in Table 2 and the results of encoder are as shown in Figure 9 and it is verified using truth Table 2.
A rampshaped analogue input signal between −0.45 and 0.75 V, at 1 MHz, is applied to the ADC input for transient analysis and the simulation results of 5bit flash ADC obtained are as shown in Figure 10. Figure 11 shows the following linearity plots of differential nonlinearity (DNL) and integral nonlinearity (INL). Transistor count of the designed system blocks is shown in Table 4. The RC extracted layout of the complete converter is shown in Figure 12. The advantages of this flash ADC are as follows: power consumption is at minimum, errors in the design are minimized, and the proposed configuration is designed at the high sampling rate 5GS/s. The performance summary and its comparison with similar works in the literature are listed in Table 5 given below.


4. Conclusion
A 5GS/s 5bit flash ADC is designed in 180 nm CMOS technology using Cadence tools. In this flash ADC, the proposed encoder uses a logic style called DCVSL structure that improves the performance in terms of power consumption and speed. The proposed flash ADC is highly linear with worstcase DNL of −0.24 LSB and INL of −0.30 LSB and also has a low power consumption of 46.69 mW. This circuit can be expected to find wider applications in many applied electronics, communications, instrumentation, and signal processing applications.
Conflict of Interests
The authors declare that there is no conflict of interests regarding the publication of this paper.
References
 G. T. Varghese and K. K. Mahapatra, “A high speed low power encoder for a 5 bit flash ADC,” in Proceedings of the International Conference on Green Technologies (ICGT '12), pp. 41–45, Trivandrum, India, December 2012. View at: Publisher Site  Google Scholar
 M. Rahman, K. L. Baishnab, and F. A. Talukdar, “A novel ROM architecture for reducing bubble and metastability errors in high speed flash ADCs,” in Proceedings of the 20th International Conference on Electronics Communications and Computers (CONIELECOMP '10), pp. 15–19, Cholula, Mexico, February 2010. View at: Publisher Site  Google Scholar
 N. Agrawal and R. Paily, “An improved ROM architecture for bubble error suppression in high speed flash ADCs,” in Proceeding of the Annual IEEE Student Paper Conference (AISPC ’08), pp. 1–5, Aalborg, Denmark, February 2008. View at: Publisher Site  Google Scholar
 Y. Z. Lin, Y. T. Liu, and S. J. Chang, “A 5bit 4.2GS/s flash ADC in 0.13$\mu $m CMOS,” in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC '07), pp. 213–216, September 2007. View at: Publisher Site  Google Scholar
 S. Park, Y. Palaskas, and M. P. Flynn, “A 4GS/s 4bit flash ADC in 0.18 μm CMOS,” IEEE Journal of SolidState Circuits, vol. 42, no. 9, pp. 1865–1872, 2007. View at: Publisher Site  Google Scholar
 K. Makigawa, K. Ono, T. Ohkawa, K. Matsuura, and M. Segami, “A 7bit 800Msps 120mW folding and interpolation ADC using a mixedaveraging scheme,” in Proceeding of the Symposium on VLSI Circuits Digest of Technical Papers (VLSIC ’06), pp. 138–139, Honolulu, Hawaii, USA, June 2006. View at: Google Scholar
 C. Chen and J. Ren, “An 8bit 200MSample/s folding and interpolating ADC in 0.25 mm^{2},” Analog Integrated Circuits and Signal Processing, vol. 47, no. 2, pp. 203–206, 2006. View at: Publisher Site  Google Scholar
 H. Y. Huang, Y. Z. Lin, and S. J. Chang, “A 5bit 1 GSample/s twostage ADC with a new flash folded architecture,” in Proceedings of the IEEE Region 10 Conference (TENCON '07), pp. 1–4, Taipei, Taiwan, November 2007. View at: Publisher Site  Google Scholar
 W. S. Chu and K. W. Current, “A CMOS voltage comparator with railtorail inputrange,” Analog Integrated Circuits and Signal Processing, vol. 19, no. 2, pp. 145–149, 1999. View at: Publisher Site  Google Scholar
 A. Srinivasulu and K. Sivadasan, “Optical exclusiveOR gate,” Journal of Microwaves, Optoelectronics and Electromagnetic Applications, vol. 3, no. 1, pp. 20–25, 2003. View at: Google Scholar
 Saloni, M. Goswami, and B. R. Singh, “A 5bit 1.5 GS/s ADC using reduced comparator architecture,” in Proceedings of the 8th International Design and Test Symposium (IDT ’13), pp. 1–3, Marrakesh, Morocco, December 2013. View at: Publisher Site  Google Scholar
 D. W. Kang and Y.B. Kim, “Design of enhanced differential cascade voltage switch logic (EDCVSL) circuits for highfanin gate,” in Proceedings of the 15 th Annual IEEE International ASIC/SOC Conference, pp. 309–313, 2002. View at: Google Scholar
 C. C. Chen, Y. L. Chung, and C. I. Chiu, “6b 1.6GS/s flash ADC with distributed trackandhold precomparators in a 0.18 $\mu $m CMOS,” in Proceedings of the International Symposium on Signals, Circuits and Systems (ISSCS '09), pp. 1–4, July 2009. View at: Publisher Site  Google Scholar
 L. Wu, F. Huang, Y. Gao, Y. Wang, and J. Cheng, “A 42 mW 2 GS/s 4bit flash ADC in 0.18μm CMOS,” in Proceeding of the International Conference on Wireless Communications and Signal Processing (WCSP ’09), pp. 1–5, Nanjing, China, November 2009. View at: Publisher Site  Google Scholar
 Z. Liu, S. Jia, Y. Wang, L. Ji, and X. Zhang, “Efficient encoding scheme for folding ADC,” in Proceedings of the 9th International Conference on SolidState and IntegratedCircuit Technology (ICSICT '08), pp. 1988–1991, Beijing, China, October 2008. View at: Publisher Site  Google Scholar
 E. Sail and M. Vesterbacka, “A multiplexer based decoder for flash analogtodigital converters,” in Proceedings of the IEEE Region 10 Conference: Analog and Digital Techniques in Electrical Engineering (TENCON '04), vol. 4, pp. 250–253, November 2004. View at: Publisher Site  Google Scholar
 G. Torfs, Z. Li, J. Bauwelinck, X. Yin, G. van der Plas, and J. Vandewege, “Lowpower 4bit flash analogue to digital converter for ranging applications,” Electronics Letters, vol. 47, no. 1, pp. 20–22, 2011. View at: Publisher Site  Google Scholar
 J. Yoo, D. Lee, K. Choi, and J. Kim, “A power and resolution adaptive flash analogtodigital converter,” in Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED ’02), pp. 233–236, August 2002. View at: Publisher Site  Google Scholar
 S. Sheikhaei, S. Mirabbasi, and A. Ivanov, “A 4Bit 5 GS/s flash A/D converter in 0.18 μm CMOS,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS ’05), vol. 6, pp. 6138–6141, May 2005. View at: Publisher Site  Google Scholar
 R. Baker, H. W. Li, and D. E. Boyce, CMOS Circuit Design, Layout and Simulation, Prentice Hall, 2000.
 J. X. Ma, S. W. Sin, S.P. U, and R. P. Martins, “A powerefficient 1.056 GS/s resolutionswitchable 5bit/6bit flash ADC for UWB applications,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '06), pp. 4305–4308, May 2006. View at: Google Scholar
 P. Pallavi, N. Agarwal, Ankita, S. Kumari, and A. Srinivasulu, “Switched capacitor charge pump circuit using modified current source inverter,” in Proceedings of the 4th International Conference on Advanced Computing and Communication Technologies, pp. 826–829, 2010. View at: Google Scholar
 D. Lee, J. Yoo, K. Choi, and J. Ghaznavi, “Fat tree encoder design for ultrahigh speed flash A/D converters,” in Proceedings of the 45th Midwest Symposium on Circuits and Systems, pp. 87–90, Tulsa, Okla, USA, August 2002. View at: Google Scholar
 V. Hiremath and S. Ren, “An ultra high speed encoder for 5GSPS Flash ADC,” in Proceedings of the IEEE International Instrumentation and Measurement Technology Conference (I2MTC '10), pp. 136–141, May 2010. View at: Publisher Site  Google Scholar
 K. Uyttenhove and M. S. J. Steyaert, “A 1.8V 6bit 1.3GHz flash ADC in 0.25μm CMOS,” IEEE Journal of SolidState Circuits, vol. 38, no. 7, pp. 1115–1122, 2003. View at: Publisher Site  Google Scholar
 W. H. Ma, J. C. Kao, and M. Papaefthymiou, “A 5.5GS/s 28mW 5bit flash ADC with resonant clock distribution,” in Proceedings of the 37th European SolidState Circuits Conference (ESSCIRC '11), pp. 155–158, September 2011. View at: Publisher Site  Google Scholar
 T. V. Rao and A. Srinivasulu, “Modified level restorers using current sink and current source inverter structures for BBLPT full adder,” Radioengineering, vol. 21, no. 4, pp. 1279–1286, 2012. View at: Google Scholar
 S. Park, Y. Palaskas, A. Ravi, R. E. Bishop, and M. P. Flynn, “A 3.5 GS/s 5b flash ADC in 90 nm CMOS,” in Proceedings of the IEEE 2006 Custom Integrated Circuits Conference (CICC ’06), pp. 489–492, San Jose, Calif, USA, September 2006. View at: Publisher Site  Google Scholar
 A. Srinivasulu and M. Rajesh, “UPLD and CPTL pullup stages for differential cascode voltage switch logic,” Journal of Engineering, vol. 2013, Article ID 595296, 5 pages, 2013. View at: Publisher Site  Google Scholar
Copyright
Copyright © 2014 Taninki Sai Lakshmi et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.