Impact of Split Gate in a Novel SOI MOSFET (SPG SOI) for Reduction of Short-Channel Effects: Analytical Modeling and Simulation
In this paper a comprehensive investigation of a novel device called split-gate silicon-on-insulator MOSFET (SPG SOI MOSFET) is proposed to reduce short-channel effects (SCEs). Studying the device has been done by analytical approach and simulation. In the proposed structure the gate is split into two parts. A voltage difference exists between the two parts. It is demonstrated that the surface potential in the channel region exhibits a step function. Some improvements are obtained on parameters such as SCEs, hot-carrier effect (HCE), and drain-induced barrier lowering (DIBL). The accuracy of the results obtained by use of the analytical model is verified by ATLAS device simulation software. The obtained results of the model are compared with those of the single-gate (SG) SOI MOSFET. The simulation results show that the SPG SOI MOSFET performance is superior.
In recent years the silicon-on-insulator metal oxide semiconductor field effect transistors (SOI MOSFETs) have been regarded as good counterpart with respect to other semiconductor devices in VLSI/ULSI technology. With progress in semiconductor device technology, the device scales shrinks to submicrometer regime. When channel length shrinks to submicrometer, undesirable effects which are named short-channel effects (SCEs) will be explored. These effects occur because controllability of the gate over-channel is reduced by shrinking the channel length.
Thin-film fully depleted SOI MOSFETs have superior electrical characteristics than the bulk MOS devices, such as reduced junction capacitances, excellent latchup immunity, increased channel mobility, and reduced short-channel effects (SCEs) . However, when the channel length becomes smaller than 100 nm, SCEs will occur . By using structures such as dual material gates, multiple gates, and fin field-effect transistors (FINFETs), short-channel effects decrease [3–5]. The scaling of SOI MOSFETs has been investigated, and several SOI structures have been studied in terms of a natural length scale . An analytical model for the threshold voltage of short-channel single-gate SOI MOSFETs has been derived with considering the two-dimensional (2D) effects in both SOI and buried-oxide layers . The potential distribution has been investigated in multiple-gate SOI MOSFETs . A threshold voltage model of a mesa-isolated SOI MOSFET based on an analytical solution of the three-dimensional (3D) Poisson’s equation has been presented . The separation of variables technique is used to analytically solve the 3D Poisson’s equation with appropriate boundary conditions. The SCEs can be reduced using an inversion layer as an ultrashallow source/drain (S/D) in the sub-50 nm regime [10–16]. An analytical model of the surface potential and threshold voltage of a SOI MOSFET with electrically induced shallow S/D junctions has been presented to investigate the SCEs . The effectiveness of the dual-martial-gate (DMG) structure in fully depleted SOI MOSFETs has been investigated to suppress SCEs by developing a 2D analytical model of surface potential and threshold voltage . Also references such as [19–21] have presented new devices to suppress the short-channel effect well.
In this paper the split-gate transistor is proposed to reduce SCEs. In this structure the gate is spilt into two parts with a small gap between them. Indeed the proposed structure is like the DMG-SOI  but by a new idea. In our structure, the voltage difference between the gates will control the channel well. In this study, a SPG SOI transistor with different gate biases is considered and also an analytical model is developed to investigate the transistor performance. The model is used to calculate the surface potential distribution in the lower SOI thin film of two the gates and to investigate the exclusive characteristics of the SPG structure in suppressing SCEs such as the hot-carrier effect, DIBL, and threshold voltage () roll-off in SOI MOSFETs. Also this model provides an efficient tool for design and characterization of the novel SPG MOSFETs. The obtained results of analytical model are verified by ATLAS software . Two-dimensional numerical simulations of the proposed structure are done with ATLAS simulator. In addition to Poissons, and drift/diffusion equations, SRH (Shockley-Read-Hall) and Auger models are considered for generation/recombination, and also IMPACT SELB for impact ionization. These simulation methods allow taking into account carrier velocity saturation, carrier-carrier scattering in the high doping concentration, and constant mobility.
2. Analytical Model
A cross-section view of a fully depleted SPG SOI MOSFET is illustrated in Figure 1 with two gates, and , of lengths and , respectively. There is a small gap of length between the gates. We assume that the impurity density in the channel region is uniform, and the effects of charge carriers and fixed oxide charges on the electrostatics of the channel can be neglected. With these assumptions the potential distribution in the silicon thin film before the onset of strong inversion can be written as where is the silicon film doping concentration, is the dielectric constant of silicon, is the film thickness, and is the device channel length. If the channel length, silicon thickness, and oxide gate thickness become very small, then the current analytical approach is not true, and the quantum models must be regarded. Also silicon thickness must not be very much because the structure is fully depleted. Also higher doping in source/drain is not very critical because the channel under the gate is very important for the structures usually.
The potential profile in the vertical direction, that is, the -dependence of can be approximated by a simple parabolic function as proposed by Young for fully depleted SOI MOSFETs : where is the surface potential and the arbitrary coefficients and are functions of only. Since the gap length () is extremely small, we assume that the potential distribution in the region of and (under the gap) for each is a linear function of . At , this potential distribution in region of reads where the coefficients and are constant values. Since we just need the potential at , (3) is true. Because of the same gate metals, the work functions of the two gates are equal. Therefore, the flat-band voltages for the two gates are the same: The semiconductor work function can be written as is the Fermi potential. is the silicon band gap. is the electron affinity. is the thermal voltage. is the intrinsic carrier concentration.
In the SPG SOI structure, the potential under the gates can be written as Poisson’s equation is solved separately under the two gates using the following boundary conditions.
The electric flux at the gate/front oxide interface is continuous for both gates: where is the dielectric constant of the oxide, is the gate oxide thickness, , and .
Note that is the gate ()-source bias voltage, is the gate ()-source bias voltage, and is the flat band voltage of and .
The electric flux at the interface of the buried oxide and back-channel silicon is continuous for both gates: where is the buried-oxide thickness and is the potential distribution along the back-side oxide-silicon interface. . is the substrate bias and is the back-channel flat-band voltage. is set to 0 V.
The surface potential at the interface of the two gates and the gap is continuous:
The electric flux at the interface of the two gates and the gap is continuous:
The potential at the source end is
The potential at the drain end is is the built-in potential across the body-source junction.
The constants , , , and in (6) can be obtained from the boundary conditions in (7)–(10). With substituting these values in (6) and then in (1), we obtain where and are obtained by solving the differential equations in (15). Finally, the surface potential distribution is obtained as where and .
By use of the boundary conditions in (11)–(14) and (17)–(19), we reach a system of six equations and unknowns.
The constant coefficients , , , , , and are calculated by solving this system of six equations and unknowns. The surface potential along the channel can be calculated with the help of these variables.
The electric field along the channel determines the electron transport velocity. The electric field components in the -direction, under the , , and the gap, are given as
3. Simulation Results and Comparison with Analytical Results
It is important that each analytical model applied in the devices must be verified by simulation software. Therefore in this paper the analytical model and simulation results have been brought and compared.
In all simulations, (gap length) is assumed to be 0.01 μm and the channel length is .
To verify our analytical model, the ATLAS device simulation software has been used to simulate the surface potential distribution within the silicon thin film. A fully depleted (FD) n-channel SPG SOI structure is implemented in ATLAS having uniformly doped source/drain and body regions.
In this study the voltage difference between the two gates is assumed to be 0.75 V, that is, . This voltage difference can be obtained by a normal diode. In Table 1 parameters needing simulation of two transistors (SPG and SG transistors) have been listed.
In Figure 2, the surface potential profile has been plotted along the horizontal distance in the channel for a channel length (, , and ) at different biases. It can be seen from this figure that, in the SPG structure, there is no significant change in the potential under the gate as the drain bias is increased. Therefore the channel region under is “screened” from the changes in the drain potential, that is, the drain voltage is not absorbed under . The DIBL effect can be demonstrated by plotting the surface potential minimum as a function of the position along the channel for different drain bias conditions. It is evident from the figure that the shift in the point of the potential minimum is almost zero. This is a clear proof that the DIBL effect is considerably reduced for the SPG SOI MOSFET.
As shown in Figure 2, the ATLAS simulation results verify the accuracy of our proposed analytical model.
In Figure 3, the electric field distributions along the channel near the drain are shown for SPG and SG SOI MOSFETs with a channel length (, , and ). As shown in this figure, the peak electric field at the drain end for the SPG SOI MOSFET is less than that for the SG SOI MOSFET. It is evident from this figure that the presence of a voltage difference between and reduces the peak electric field considerably. Therefore hot-carrier effect in SPG SOI MOSFET is less than that for the SG SOI MOSFET. The results of the analytical model are in close proximity with the ATLAS simulation results.
Figure 4 shows the surface potential profiles along the channel position for different gate length ratios of to (). The sum of the channel length () is constant. As shown in the figure, by reducing the length , the position of the potential minimum shifts toward the source. This causes the peak electric field in the channel to shift toward the source end and thus results in a more uniform electric field profile in the channel. This redistributes the surface potential, which results in a more uniform potential along the channel. Note that cannot be reduced to a very small value, since in the case of , we have a SG transistor with a gate bias that is higher than the applied gate bias . This higher gate bias reduces to a very small value and therefore increases the off current.
In Figure 5 the variations in potential minimum as a function of the channel length with constant for fully depleted SPG and SG SOI MOSFETs with silicon film thicknesses and 20 nm are shown. In the case of the SPG SOI MOSFET, the dependence of the potential minimum on the silicon thin-film thickness reduces with decreasing . This is due to the existence of a voltage difference between the two gates in SPG structure. The validity of model for the surface potential minimum under the gate for different combinations of and is verified by ATLAS simulation results.
In Figure 6 the threshold voltage has been shown as a function of the channel length with constant . was obtained for two structures SPG SOI MOSFET and SG SOI MOSFET with help of ATLAS simulator. The threshold voltage is extracted by calculating the maximum slope of the curve, finding the intercept with the axis, and then subtracting half of the applied drain bias .
As shown in this figure, the variations in threshold voltage for SPG SOI MOSFET are less than, those of the SG SOI MOSFET. Therefore DIBL is reduced in SPG SOI. Also we have a desirable rollup in the threshold voltage with reducing channel length for SPG SOI MOSFET. Note that when the threshold voltage with shrinking channel length increases, off-current variations decreases, and this is a good benefit. But in the SG SOI MOSFET the threshold voltage decreases, with shrinking channel length. This results in increasing the off-current variations in the SG SOI MOSFET structure. Therefore the performance of SPG SOI MOSFET is superior to that in SG SOI MOSFET.
The impact of the split gate in fully depleted SOI MOSFETs has been examined to suppress SCEs by developing a 2-D analytical model for surface potential and by comparing the results with ATLAS device simulation software. In the proposed transistor (SPG transistor) a voltage difference is introduced between the two gates. In SPG structure, the shift in the surface channel potential minimum position is negligible with increasing the drain bias. The electric field in the channel at the drain end is reduced. Therefore the hot-carrier effect reduces. The DIBL effect in our transistor is reduced because the voltage difference between the two gates is applied. In addition, the variation in the channel potential minimum with decreasing film thickness in our transistor is less than that in the SG SOI MOSFET. Also we obtained a desirable rollup in the threshold voltage with decreasing channel length for SPG SOI MOSFET. All obtained results of analytical model have been verified by ATLAS simulation software. These results show that the analytical model in SPG transistor is completely proper and also the SPG transistor performance is superior to that SG transistor.
T. Ohno, Y. Kado, M. Harada, and T. Tsuchiya, “Experimental 0.25-μm-gate fully depleted CMOS/SIMOX process using a new two-step LOCOS isolation technique,” IEEE Transactions on Electron Devices, vol. 42, no. 8, pp. 1481–1486, 1995.View at: Publisher Site | Google Scholar
O. C. Adelmo, J. G. S. F. Sánchez, M. Juan, M. Slavica, and J. L. Juin, “A review of core compact models for undoped double-gate SOI MOSFETs,” IEEE Transactions on Electron Devices, vol. 54, no. 1, pp. 131–140, 2007.View at: Publisher Site | Google Scholar
W. Long, H. Ou, J. M. Kuo, and K. K. Chin, “Dual material gate(DMG) field effect Transistor,” Transactions on Electron Devices, vol. 46, pp. 865–870, 1999.View at: Google Scholar
R. Granzner, F. Schwierz, and V. M. Polyakov, “An analytical model for the threshold voltage shift caused by two-dimensional quantum confinement in undoped multiple-gate MOSFETs,” IEEE Transactions on Electron Devices, vol. 54, no. 9, pp. 2562–2565, 2007.View at: Publisher Site | Google Scholar
D. Hisamoto, W. C. Lee, J. Kedzierski et al., “FinFET-A selfaligned doublegate MOSFET scaleable to 20 nm,” Transactions on Electron Devices, vol. 47, pp. 2320–2325, 2000.View at: Google Scholar
R. H. Yan, A. Ourmazd, and K. F. Lee, “Scaling the Si MOSFET: from bulk to SOI to bulk,” IEEE Transactions on Electron Devices, vol. 39, no. 7, pp. 1704–1710, 1992.View at: Publisher Site | Google Scholar
K. Suzuki and S. Pidin, “Short-channel single-gate SOI MOSFET model,” IEEE Transactions on Electron Devices, vol. 50, no. 5, pp. 1297–1305, 2003.View at: Publisher Site | Google Scholar
J. P. Colinge, “Multiple-gate SOI MOSFETs,” Solid-State Electronics, vol. 48, no. 6, pp. 897–905, 2004.View at: Publisher Site | Google Scholar
G. Katti, N. DasGupta, and A. DasGupta, “Threshold voltage model for mesa-isolated small geometry fully depleted SOI MOSFETs based on analytical solution OF 3-D poisson's equation,” IEEE Transactions on Electron Devices, vol. 51, no. 7, pp. 1169–1177, 2004.View at: Publisher Site | Google Scholar
H. Kawaura, T. Sakamoto, T. Baba et al., “Transistor operation of 30-nm gate-length EJ-MOSFETs,” IEEE Electron Device Letters, vol. 19, no. 3, pp. 74–76, 1998.View at: Google Scholar
S. Han, S. I. Chang, J. Lee, and H. Shin, “50 nm MOSFET with electrically induced source/drain (S/D) extensions,” IEEE Transactions on Electron Devices, vol. 48, no. 9, pp. 2058–2064, 2001.View at: Publisher Site | Google Scholar
H. Noda, F. Murai, and S. I. Kimura, “Threshold voltage controlled 0.1-μm MOSFET utilizing inversion layer as extreme shallow source/drain,” in Proceedings of the IEEE International Electron Devices Meeting, pp. 123–126, December 1993.View at: Google Scholar
W. Xusheng, Z. Shendong, M. Chan, and P. Chan, “Design of Sub-50 nm ultrathin-body (UTB) SOI MOSFETs with raised S/D,” in Proceedings of the IEEE Conference on Electron Devices and Solid-State Circuits, pp. 251–254, 2003.View at: Google Scholar
A. Hartstein, N. F. Albert, A. A. Bright, S. B. Kaplan, B. Robinson, and J. A. Tornello, “A metal-oxide-semiconductor field-effect transistor with a 20-nm channel length,” Journal of Applied Physics, vol. 68, no. 5, pp. 2493–2495, 1990.View at: Publisher Site | Google Scholar
H. S. Wong, “Experimental verification of the mechanism of hot-carrier induced photon emission in N-MOSFETs with a CCD gate structure,” in Proceedings of the International Electron Devices Meeting (IEDM '91), pp. 549–552, 1991.View at: Google Scholar
P. S. T. Chang, Y. Kohyama, M. Kakuma et al., “High performance deep submicron buried channel PMOSFET using P++ poly-Si spacer induced self-aligned ultra shallow junctions,” in Proceedings of the IEEE International Electron Devices Meeting (IEDM '92), pp. 905–908, 1992.View at: Google Scholar
M. J. Kumar and A. A. Orouji, “Two-dimensional analytical threshold voltage model of nanoscale fully depleted SOI MOSFET with electrically induced S/D extensions,” IEEE Transactions on Electron Devices, vol. 52, no. 7, pp. 1568–1575, 2005.View at: Publisher Site | Google Scholar
M. J. Kumar and A. Chaudhry, “Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs,” IEEE Transactions on Electron Devices, vol. 51, no. 4, pp. 569–574, 2004.View at: Publisher Site | Google Scholar
S. E. Hosseini, “Split gate SOI MOSFET with drain dependent bias for short channel effects reduction,” in Proceedings of the International Conference on Signal Processing Systems (ICSPS '09), pp. 863–865, May 2009.View at: Publisher Site | Google Scholar
Q. Jiang, M. Wang, and X. Chen, “A high-speed deep-trench MOSFET with a self-biased split gate,” IEEE Transactions on Electron Devices, vol. 57, no. 8, pp. 1972–1977, 2010.View at: Publisher Site | Google Scholar
J. Yuan and J. C. S. Woo, “A novel split-gate MOSFET design realized by a fully silicided gate process for the improvement of transconductance and output resistance,” IEEE Electron Device Letters, vol. 26, no. 11, pp. 829–831, 2005.View at: Publisher Site | Google Scholar
Device Simulator ATLAS, Silvaco, Sanata Clara, Calif, USA, 2012.
K. K. Young, “Short-channel effect in fully depleted SOI MOSFET's,” IEEE Transactions on Electron Devices, vol. 36, no. 2, pp. 399–402, 1989.View at: Publisher Site | Google Scholar