Differential Difference Current Conveyor Transconductance Amplifier: A New Analog Building Block for Signal Processing

Abstract

A new active building block for analog signal processing, namely, differential difference current conveyor transconductance amplifier (DDCCTA), is presented, and performance is checked through PSPICE simulations which show the usability of the proposed element is up to 201 MHz. The proposed block is implemented using 0.25 μm TSMC CMOS technology. Some of the applications are presented using the proposed DDCCTA, namely, a voltage mode multifunction filter, a current mode universal filter, an oscillator, current and voltage amplifiers, and grounded inductor simulator. The feasibility of DDCCTA and its applications is confirmed via PSPICE simulations.

1. Introduction

The analog integrated circuit design in current mode is receiving increased attention due to some potential performance features like wide bandwidth, less circuit complexity, wide dynamic range, low power consumption, and high operating speed [1]. The current mode approach has emerged as an alternate method besides the traditional voltage mode circuits. The current mode active elements are appropriate to operate with signals in current or voltage or mixed mode and are gaining acceptance as building blocks in high-performance circuit designs. A number of current mode active elements such as operational transconductance amplifier (OTA) [2], current conveyors (CCs) [3–5], differential voltage current conveyor (DVCC) [6], differential difference current conveyor (DDCC) [7], current feedback operational amplifier (CFOA) [8] are available in the literature.

Recently some new analog building blocks, such as current conveyor transconductance amplifier (CCTA) [9, 10], current controlled current conveyor transconductance amplifier (CCCCTA) [11], current difference transconductance amplifier (CDTA) [12], current controlled current difference transconductance amplifier (CCCDTA) [13], differential voltage current conveyor transconductance amplifier (DVCCTA) [14], and differential voltage current controlled conveyor transconductance amplifier (DVCCCTA) [15], are reported in the literature. These may be constructed by cascading of current mode building blocks with transconductance amplifier (TA) analog building blocks in monolithic chip for compact implementation of signal processing circuits and systems. It is well known that DDCC has some advantages [7, 16, 17] specially for applications demanding differential and floating inputs, over CCII or CCCII owing to three high input impedance terminals for DDCC compared to one high input impedance terminal for CCII or CCCII. However, DDCC does not have a powerful inbuilt tuning property in contrast to CCCII. The DDCC is more versatile than DVCC as it has an extra high input impedance terminal.

The main intention of this paper is to propose a new active building block, namely, differential difference current conveyor transconductance amplifier (DDCCTA), which has DDCC [7] as input block and is followed by a TA. The DDCCTA has all the good properties of CCTA, CCCCTA, and DVCCTA including the possibility of inbuilt tuning of the parameters of the signal processing circuits to be implemented and also all the versatile and special properties of DDCC such as easy implementation of differential and floating input circuits. However, the same may be implemented using separate DDCC and OTA analog building blocks, but it will be more convenient and useful if DDCCTA is implemented in monolithic chip which will result in compact implementation of signal processing circuits and systems. Section 2 deals with the proposed DDCCTA circuit and some of its properties. Section 3 is devoted for some of its applications in developing signal processing circuits such as voltage mode (VM) filter, current mode (CM) filter, oscillator, current and voltage amplifier, and grounded inductor simulator. The functionality of all the proposed circuits has been verified using SPICE simulations. The conclusion is given in Section 4.

2. Proposed DDCCTA

The DDCCTA is based on DDCC [7] and consists of differential amplifier, current mirrors, and TA. The port relationships of the DDCCTA as shown in Figure 1 can be characterized by the following matrix: ⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣𝐼_𝑌1𝐼_𝑌2𝐼_𝑌3𝑉_𝑋𝐼_𝑍1+𝐼_𝑍2+𝐼₀₁₋𝐼_𝑂2−⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦=⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣0001000−000000100010000000110−000000𝑔_𝑚0000000000000000000000−𝑔_𝑚000000⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦×⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣𝑉^𝑌1𝑉_𝑌2𝑉_𝑌3𝐼_𝑋𝑉_𝑍1+𝑉_𝑍2+𝑉_𝑂1−𝑉_𝑂2−⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦,(1) where 𝑔_𝑚 is transcon/ductance of the DDCCTA.

Figure 1 

Circuit symbol of the proposed DDCCTA.

The CMOS-based internal circuit of DDCCTA in CMOS is depicted in Figure 2. It consists of the circuit of DDCC [7] (transistors M1 to M14) followed by a transconductance amplifier (transistors M15 to M24). The derivation of port relationships is given in Sections 2.1 to 2.3 [13].

Figure 2 

DDCCTA implementation.

2.1. Relationship between Voltages of 𝑋 Port and 𝑌1, 𝑌2, and 𝑌3 Ports

The voltage at 𝑋 port may be found by analyzing the differential difference part (comprising of transistors M1 to M10) of the circuit of Figure 2 as follows:𝑉_𝑋=𝛽₁𝑉_𝑌1−𝛽₂𝑉_𝑌2+𝛽𝑉_𝑌3+𝜀_𝑉,(2) where𝛽₁=1𝑃₁𝑔^𝑚3𝑔_𝑚6+𝑔^𝑚3𝑔_𝑚4𝑔_𝑚5−𝑔_𝑚3𝑔_𝑚6𝛽₂𝑔_𝑚3+𝑔_𝑚4,=1𝑃₁𝑔^𝑚1𝑔_𝑚5+𝑔^𝑚1𝑔_𝑚1𝑔_𝑚5−𝑔_𝑚2𝑔_𝑚6𝛽₃𝑔_𝑚1+𝑔_𝑚2,=1𝑃₁𝑔^𝑚2𝑔_𝑚6+𝑔^𝑚2𝑔_𝑚1𝑔_𝑚5−𝑔_𝑚2𝑔_𝑚6𝜀_𝑉𝑔_𝑚1+𝑔_𝑚2,=−𝐼^𝐵𝑃₁𝑔^𝑚1𝑔_𝑚5−𝑔_𝑚2𝑔_𝑚6𝑔_𝑚1+𝑔_𝑚2+𝑔^𝑚4𝑔_𝑚5−𝑔_𝑚3𝑔_𝑚6𝑃₁𝑔_𝑚3+𝑔_𝑚4,=𝑔_𝑚4𝑔_𝑚5−𝑔^𝑚4𝑔_𝑚4𝑔_𝑚5−𝑔_𝑚3𝑔_𝑚6𝑔_𝑚3+𝑔_𝑚4,(3) and 𝐼_𝐵 represents current through transistor Mi (𝑖=7,8,10,12,14). With matched transconductances 𝑔_𝑚1=𝑔_𝑚2=𝑔_𝑚3=𝑔_𝑚4 and 𝑔_𝑚5=𝑔_𝑚6, 𝑉_𝑋 is obtained as𝑉_𝑋=𝑉_𝑌1−𝑉_𝑌2+𝑉_𝑌3.(4)

2.2. Relationship between Currents at 𝑍1+, 𝑍2+, and 𝑋 Ports

The analysis of the portion of the circuit comprising of transistors M9 to M14 of the circuit of Figure 2 gives𝐼𝐼_𝑍1+𝑍2+=𝛼₁𝐼_𝑋+𝜀_𝐼1,=𝛼₂𝐼_𝑋+𝜀_𝐼2,(5) where𝛼₁=𝑔^𝑚11𝑔_𝑚9,𝜀_𝐼1=1−𝑔^𝑚11𝑔_𝑚9𝐼^𝐵𝛼₂,=𝑔^𝑚13𝑔_𝑚9,𝜀_𝐼2=1−𝑔^𝑚13𝑔_𝑚9𝐼^𝐵.(6) For matched transconductances 𝑔_𝑚9=𝑔_𝑚11=𝑔_𝑚13, the port currents are simplified to 𝐼_𝑍1+=𝐼_𝑍2+=𝐼_𝑋.(7)

2.3. Relation for Currents at 𝑂1− and 𝑂2− Ports

The proposed DDCCTA contains a transconductor cell comprising of transistors M15 to M24. Assuming gate voltages of transistors M17 and M18 as 𝑉_𝑇1 and 𝑉_𝑇2, the output currents 𝐼_𝑂1− and 𝐼_𝑂2− may be found, respectively, as𝐼𝐼_{𝑂1−𝑂2−}=−𝛾₁𝑉_𝑇1−𝛾₂𝑉_𝑇2+𝜀_𝑇1,=−𝛾₃𝑉_𝑇1−𝛾₄𝑉_𝑇2+𝜀_𝑇2,(8) where𝛾₁=𝑔_𝑚17𝑔^𝑚16𝑔_𝑚22𝑔_𝑚15𝑔_𝑚21−1𝑔_𝑚15𝑔_𝑚19𝑔_𝑚21×𝑔^𝑚16𝑔_𝑚17𝑔_𝑚19𝑔_𝑚22−𝑔_𝑚15𝑔_𝑚18𝑔_𝑚20𝑔_𝑚21𝛾𝑔_𝑚17+𝑔_𝑚18₂,=𝑔_𝑚18𝑔𝑔^𝑚20_𝑚19+1𝑔_𝑚15𝑔_𝑚19𝑔_𝑚21×𝑔^𝑚16𝑔_𝑚17𝑔_𝑚19𝑔_𝑚22−𝑔_𝑚15𝑔_𝑚18𝑔_𝑚20𝑔_𝑚21𝛾𝑔_𝑚17+𝑔_𝑚18₃,=𝑔_𝑚17𝑔^𝑚16𝑔_𝑚24𝑔_𝑚15𝑔_𝑚21−1𝑔_𝑚15𝑔_𝑚19𝑔_𝑚21×𝑔^𝑚16𝑔_𝑚17𝑔_𝑚19𝑔_𝑚24−𝑔_𝑚15𝑔_𝑚18𝑔_𝑚23𝑔_𝑚21𝛾𝑔_𝑚17+𝑔_𝑚18₄,=𝑔_𝑚18𝑔𝑔^𝑚23_𝑚19+1𝑔_𝑚15𝑔_𝑚19𝑔_𝑚21×𝑔^𝑚16𝑔_𝑚17𝑔_𝑚19𝑔_𝑚24−𝑔_𝑚15𝑔_𝑚18𝑔_𝑚23𝑔_𝑚21𝜀𝑔_𝑚17+𝑔_𝑚18_𝑇1,=−𝐼^Bias𝑔_𝑚15𝑔_𝑚19𝑔_𝑚21×𝑔^𝑚16𝑔_𝑚17𝑔_𝑚19𝑔_𝑚22−𝑔_𝑚15𝑔_𝑚18𝑔_𝑚20𝑔_𝑚21𝜀_𝑇2𝑔_𝑚17+𝑔_𝑚18,=−𝐼^Bias𝑔_𝑚15𝑔_𝑚19𝑔_𝑚21×𝑔^𝑚16𝑔_𝑚17𝑔_𝑚19𝑔_𝑚24−𝑔_𝑚15𝑔_𝑚18𝑔_𝑚23𝑔_𝑚21𝑔_𝑚17+𝑔_𝑚18.(9) With 𝑔_𝑚17=𝑔_𝑚18, 𝑔_𝑚21=𝑔_𝑚22=𝑔_𝑚24, 𝑔_𝑚15=𝑔_𝑚16=𝑔_𝑚19=𝑔_𝑚20=𝑔_𝑚23, the output currents 𝐼_𝑂1− and 𝐼_𝑂2− reduce to𝐼𝐼_𝑂1−=−𝑔_𝑚17𝑉_𝑇1−𝑔_𝑚18𝑉_𝑇2,(10)_𝑂2−=−𝑔_𝑚17𝑉_𝑇1−𝑔_𝑚18𝑉_𝑇2.(11) In the circuit, 𝑉_𝑇1=𝑉_𝑍1+ and 𝑉_𝑇2=0; hence the output currents are simplified to 𝐼_𝑂1−=−𝑔_𝑚17𝑉_𝑍1+,𝐼_𝑂2−=−𝑔_𝑚17𝑉_𝑍1+.(12)

The value of 𝑔_𝑚17 is obtained as √2𝜇𝐶_ox(𝑊/𝐿)₁₇𝐼_Bias if transistors are biased in strong inversion region and 2𝐼_Bias/𝑉_𝑇(𝑉_𝑇=𝐾𝑇/𝑞) if transistors are biased in subthreshold region which can be adjusted by bias current 𝐼_Bias.

2.4. Simulation

To validate the behaviour of the proposed element, PSPICE simulations have been carried out using TSMC 0.25 μm CMOS process model parameters. The supply voltages of 𝑉_DD=−𝑉_SS=1.25 V and 𝑉_BB=−0.8 V are used. The aspect ratio of various transistors for DDCCTA is given in Table 1. The DC transfer characteristics of the proposed DDCCTA from 𝑌1, 𝑌2, and 𝑌3 terminals to 𝑋 terminal are shown in the Figure 3. It is clear that the voltage at 𝑋 terminal follows the 𝑌 terminal voltages in the range of −200 mV to +200 mV. The variation of current at 𝑍1+ and 𝑍2+ terminals with 𝑋 terminal current from −100 μA to 100 μA is shown in Figure 4. It may be noted that there is deviation for current below −80 μA. The variation of the transconductance value by changing 𝐼_Bias from 0 to 500 μA is depicted in Figure 5. The decreases in transconductance for larger bias currents than 450 μA or so is due to transistors (M₁₇, M₁₈) entering in linear region of operation from saturation region. The maximum transconductance is about 1.6 mS. The other circuit performance parameters of the DDCCTA are summarised in Table 2.

Table 1 

Aspect ratio of various transistors.

Table 2 

Circuit performance parameters of the DDCCTA.

(a)

(b)

(c)

Figure 3 

DC transfer characteristic for voltage transfer from (a) 𝑌1 port to 𝑋 port, (b) 𝑌2 port to 𝑋 port, and (c) 𝑌3 port to 𝑋 port.

Figure 4 

DC transfer characteristic for current transfer from 𝑋 port to 𝑍1+ and 𝑍2+ ports.

Figure 5 

Variation of transconductance with bias current.

3. Applications

3.1. Multifunction Voltage Mode Filter

In this section a multifunction voltage mode (VM) filter is proposed. It uses a single DDCCTA, two grounded capacitors, and a grounded resistor. The proposed multifunction VM filter is shown in Figure 6. The analysis of circuit yields the output voltages at various nodes as𝑉_out1𝑉_in=𝑠²𝐶₁𝐶₂𝑅𝑉𝐷(𝑠)_out2,𝑉_in=𝑠𝐶²𝑉𝐷(𝑠)_out3,𝑉_in=−𝑔^𝑚𝐷(𝑠),(13) where𝐷(𝑠)=𝑠²𝐶₁𝐶₂𝑅+𝑠𝐶₂+𝑔_𝑚.(14)

Figure 6 

Proposed voltage mode filter.

It may be observed from (13) that high-pass, band-pass, and low-pass responses are available simultaneously at 𝑉_out1, 𝑉_out2, and 𝑉_out3, respectively. Thus, the proposed structure is a single-input-and-three-output voltage mode filter. It may be noted that no component matching constraint is required. The responses are characterized by pole frequency (𝜔₀), bandwidth (𝜔₀/𝑄₀), and quality factor (𝑄₀) as𝜔₀=𝑔^𝑚𝑅𝐶₁𝐶₂^1/2,𝜔⁰𝑄₀=1𝑅𝐶₁,𝑄₀=𝑔^𝑚𝑅𝐶₁𝐶₂^1/2.(15)

Equation (15) reveals that for high-pass and band-pass responses the pole frequency (𝜔₀) and quality factor (𝑄₀) can be adjusted by 𝑔_𝑚, that is, by bias current of DDCCTA, without disturbing 𝜔₀/𝑄₀. The 𝜔₀ and 𝑄₀ are orthogonally adjustable with simultaneous adjustment of 𝑔_𝑚 and 𝑅 such that the product 𝑔_𝑚𝑅 remains constant and the quotient 𝑔_𝑚/𝑅 varies and vice versa. The resistance 𝑅 being a grounded one may easily be implemented as a variable resistance using only two MOS [17]. Equation (15) also indicates that high values of 𝑄-factor will be obtained from moderate values of ratios of passive components, that is, from low component spread [22]. These ratios can be chosen as 𝑔_𝑚𝑅=(𝐶₁/𝐶₂)=𝑄₀. Hence, the spread of the component values becomes of the order of √𝑄₀. This feature of the filter related to the component spread allows the realization of high 𝑄₀ values more accurately compared to the topologies where the spread of passive components becomes 𝑄₀ or 𝑄²⁰. It can also be easily evaluated to show that the sensitivities of pole 𝜔₀ and pole 𝑄₀ are within unity in magnitude. Thus, the proposed structures, can be classified as insensitive.

A detailed study of the available similar type of single-active-element-based (such as CCCTA, DBTA, and DVCCCTA) voltage mode filters and the proposed one is given in Table 3. It reveals that the topology [18, 19] uses excessive number of passive components whereas the proposed topology uses one extra passive component, namely, resistor (𝑅) than [11, 15]. The proposed topology also provides the availability of a maximum number of simultaneous responses. Structures [11, 18, 19] use floating passive components and also use matching condition. Topology [11] needs input signal 𝑉_in, −𝑉_in, and −2𝑉_in; hence there is requirement of additional circuits. Thus, it reveals that although the proposed topology realizes only LP, HP, and BP responses, it has two or more advantages over the other available topologies [11, 15, 18, 19].

Table 3 

Comparative study of the available similar type of single-active-element-based VM filters.

To verify the functionality of the proposed single-DDCCTA-based voltage mode filter, SPICE simulations have been carried out using TSMC 0.25 μm CMOS process model parameters and supply voltages of 𝑉_DD=−𝑉_SS=1.25V and 𝑉_BB=−0.8V. The filter is designed for a pole frequency of 𝑓₀=1.59 MHz, 𝑄=1, the component values are found to be 𝐶₁=𝐶₂=100 pF, 𝑅=1 kΩ, and bias current of DVCCTA equals 100 μA. Figure 7 shows the simulation results for high-pass (𝑉_out1), band-pass (𝑉_out2), and low-pass (𝑉_out3) filter responses which are available simultaneously.

Figure 7 

Simulated responses of the proposed voltage mode filter.

3.2. MISO Current Mode Universal Filter

A multiple-input single-output (MISO) universal current mode (CM) filter is proposed in this section which is obtained by grounding voltage input in Figure 6 and exciting it with current inputs as shown in Figure 8. It employs a single DDCCTA, two grounded capacitors, and a grounded resistor. Analysis of this circuit gives the output current as𝐼_out1=−𝑠²𝐶₁𝐶₂𝑅𝐼_in1−𝑠𝐶₂+𝑔_𝑚𝐼_in2+𝑠𝐶₁𝐼_in3𝐼𝐷(𝑠)_out2,=𝐼ⁱⁿ¹−𝐼_in2𝑠𝐶₂𝑅𝑔_𝑚+𝑔_𝑚𝐼_in3+𝐷(𝑠)𝐼_in4𝐷(𝑠),(16) where 𝐷(𝑠)=𝑠²𝐶₁𝐶₂𝑅+𝑠𝐶₂+𝑔_𝑚.(17)

Figure 8 

Current mode universal filter.

Table 4 shows the availability of each filter response and the corresponding selection of input currents 𝐼_in1, 𝐼_in2, 𝐼_in3, and 𝐼_in4. Thus, the proposed structure is a four-input-single-output current mode filter. It may be noted that there is no component matching constraint for obtaining any filter response. The filter parameters are the same as given in (15). The grounded resistance (𝑅) may easily be implemented as variable one using only two MOS [17] for full electronic control of filter parameters. The 𝜔₀, 𝑄₀, and 𝜔₀/𝑄₀ can be orthogonally adjusted for low-pass, high-pass, and band-pass responses the way discussed in Section 3.1.

Table 4 

The 𝐼_in1, 𝐼_in2, 𝐼_in3, and 𝐼_in4 values selection for each filter function response.

A detailed study of the available similar type of active-element-based (such as CCCCTA, CCCDTA, and CCCCTA) CM filters and the proposed one is given in Table 5. It reveals that although the proposed structure needs one extra resistor, the reported structures [11, 13, 20, 21] suffer from one or more features. In addition some active elements are required to sense current in [13, 21]. Thus, structures in [11, 13, 20, 21] will require some extra circuits to compensate the shortcomings in their features in comparison to the proposed one.

Table 5 

Comparative study of the available similar type of single-active-element-based CM filters.

The proposed universal MISO current mode filter is validated through SPICE simulations. The circuit of Figure 8 for a pole frequency of 𝑓₀=1.59  MHz, 𝑄=1 has been designed with the component values of 𝐶₁=𝐶₂=100 pF, 𝑅=1 kΩ, and bias current of DDCCTA equal to 100 μA. Figure 9(a) shows the simulation results for band pass (𝐼_out1) and low pass (𝐼_out2) filter responses which are available simultaneously for 𝐼_in=𝐼_in3, 𝐼_in1=𝐼_in2=𝐼_in4=0. Figure 9(b) shows the simulation results for band pass (𝐼_out2) and high-pass (𝐼_out1) filter responses which are available simultaneously for 𝐼_in=𝐼_in1, 𝐼_in2=𝐼_in3=𝐼_in4=0. Notch and all pass responses are shown in Figures 9(c) and 9(d) with 𝐼_in=𝐼_in2=𝐼_in4, 𝐼_in1=𝐼_in3=0 and 𝑅=1 kΩ and 2 kΩ, respectively.

(a)

(b)

(c)

(d)

Figure 9 

Simulated responses of the proposed current mode universal filter: (a) low pass and band pass; (b) high pass and band pass; (c) notch; (d) all pass.

3.3. Oscillator

The current mode filter of Figure 8 may be used as oscillator when output 𝐼_out2 is connected to 𝐼_in1 as shown in Figure 10. The analysis of the circuit of Figure 10 gives the following characteristic equation:𝑠²𝐶₁𝐶₂𝑅+𝑠𝐶₂𝑅𝑔_𝑚−1+𝑔_𝑚=0.(18) The condition and frequency of oscillation may be computed as CO:𝑔_𝑚=1FO:𝜔₀𝑅,=𝑔_𝑚𝑅𝐶₁𝐶₂.(19) The oscillations are available at outputs 𝑉_out1 and 𝑉_out2, and they are related as𝑉_out1=−𝑔^𝑚𝑠𝐶₂𝑉_out2.(20) Thus, these voltages exhibit quadrature relationship. The current oscillations are also available at high output impedance at 𝐼_out.

Figure 10 

Proposed Oscillator.

To verify the proposed circuit, an oscillator was designed for 1.59 MHz with 𝐶₁=𝐶₂=100 pF, 𝑅=1 kΩ, and bias current of 100 μA. The simulated current and quadrature voltage waveforms are shown in Figure 11 for which the total harmonic distortion is 1.28%.

(a)

(b)

Figure 11 

Outputs of the proposed oscillator: (a) quadrature output voltages at 𝑉out1 and 𝑉out2; (b) current oscillation at 𝐼out.

3.4. Voltage Amplifier, Current Amplifier, and Grounded Inductor

The proposed DDCCTA may also be configured for voltage and current amplifiers and grounded inductor simulator as shown in Figures 12, 13, and 14, respectively. The transfer functions may be expressed as follows:

Figure 12 

Voltage amplifier.

Figure 13 

Current amplifier.

Figure 14 

Grounded inductor simulator.

(i) voltage amplifier: 𝑉_out𝑉_in=1𝑅𝑔_𝑚,(21)

(ii) current amplifier: 𝐼_out𝐼_in=𝑅𝑔_𝑚,(22)

(iii) grounded inductor simulator: 𝑍_in=𝑉ⁱⁿ𝐼_in=𝑠𝐶𝑅𝑔_𝑚.(23) It may be noted that the gain of amplifiers and inductance can be adjusted by 𝑔_𝑚, that is, by varying bias current of DDCCTA.

To verify the proposed amplifiers, the simulations have been carried out for 𝑅=0.5 kΩ (2 kΩ) for voltage (current) amplifier and bias current of 25 μA to 400 μA. The results are depicted in Figures 15 and 16. The inductor simulator is also validated through simulation with 𝑅=0.5 KΩ, 𝐶=100 pF, and bias current of 90 μA. Figure 17 shows the simulated and theoretical results and there is close agreement between the two.

Figure 15 

Voltage gain.

Figure 16 

Current gain.

Figure 17 

Frequency response of grounded inductor.

4. Conclusion

A new analog building block, namely, DDCCTA, is presented and some of its properties are discussed. It is found that the proposed DDCCTA is useful up to about 201 MHz. As applications of the proposed DDCCTA, VM multifunction filter, CM universal filter, quadrature oscillator, voltage and current amplifiers, and grounded inductor simulator topology are presented. The resistor being grounded may easily be implemented as a variable one using only two MOS [17]. The simulation results verify the theory.