Abstract
A single channel 2 GSps, 8-bit folding and interpolation (F&I) analog-to-digital converter (ADC) with foreground calibration in TSMC 90 nm CMOS technology is presented in this paper. The ADC utilizes cascaded folding, which incorporates an interstage sample-and-hold amplifier between the two stages of folding circuits to enhance the quantization time. A master-slave track-and-hold amplifier (THA) with bootstrapped switch is taken as the front-end circuit to improve ADC’s performance. The foreground digital assisted calibration has also been employed to correct the error of zero-crossing point caused by the circuit offset, thus improving the linearity of the ADC. Chip area of the whole ADC including pads is 930 μm × 930 μm. Postsimulation results demonstrate that, under a single supply of 1.2 volts, the power consumption is 210 mW. For the sampling rate of 2 GSps, the signal to noise and distortion ratio (SNDR) is 45.93 dB for Nyquist input signal.
1. Introduction
High-speed (GSps), media-resolution (6~8 b), and low power analog-to-digital converters (ADCs) are essential in realizing high-speed communication systems, test equipment, radar, and radio astronomy systems. For example, the millimeter-wave-based wireless personal area network (WPAN) allows very high data rate application (>2 Gbps). Multi-GSps and 5~8-bit ADCs are highly demanded and essential in these systems [1]. Another example would be that high-speed ADCs are the core elements in the digital oscilloscopes; they usually have a resolution of more than 8 bits and a sampling rate of over 1 GSps, even 20 GSps [2]. However, increased device mismatch, decreased supply voltage, and excessive power consumption prevent current GSps single channel CMOS converters from being extended to 8 bits. Flash and folding ADCs are the primary candidates for GSps applications due to their high conversion speed and low latency. Although the flash architecture has been used in the highest speed ADCs, it suffers from the severe disadvantage that it requires comparators for bits of resolution, which results in a substantial area and power penalty starting at the 8 b level. As a result, pipelined folding and interpolation (F&I) has been adopted in our proposed design of 2 GSps, 8-bit ADC.
For medium and high resolution ADCs, the folding factor and interpolation factor should be large as the comparators and folding amplifiers can be eliminated by a factor of and , respectively. However, it is inappropriate to realize large folding and interpolation factor in a single stage. Therefore, cascaded folding and interpolation should be taken. In the proposed design, folding and interpolation factors have been selected to be and to balance the system area, the speed, and the performance. Interstage sample-and-hold amplifiers (SHAs) are adopted to enhance the quantization time. Foreground digital assisted calibration is also adopted to improve the performance of ADC caused by device mismatch, the impact of gain error, and other nonideal factors, while at the same time it uses the small sized transistors in order to maintain its speed advantage.
The rest of the paper is organized as follows. In the next section, key circuits and digital calibration of the ADC will be presented; Section 3 shows the layout and system simulation results of the design. Conclusions will be drawn in Section 4, and acknowledgements are in the last section.
2. Circuit of the Proposed ADC
The proposed ADC is a single channel circuit as shown in Figure 1. The upper part is the main circuit and the under part is the calibration circuit. For the main circuit, the coarse and the fine channel quantify the signal from the front-end track-and-hold amplifier (THA), respectively, and deliver the quantization signal to the 8 D Flip-Flop (DFFs) to get the final results. The fine channel is much more complicated than the coarse channel. It is composed of 19 preamps (1 for redundancy), two F&I stages (6 for the first stage with folding factor and interpolation factor ; 4 for the second stage with folding factor and interpolation factor ), and 12-interstage SHA to enhance the quantization time, 32 comparators, and 32-spark code elimination circuit and fine coding circuit. The coarse channel is composed of 6 preamps, 6 comparators, 7 DFFs, and coarse coding. There is also a synchronization circuit to make sure that the result is correct.
The under part is the calibration circuit and it includes the logic control, the counter, the DFF array, and the digital-to-analog converters (DACs). This will be explained further in Section 2.4.
2.1. The Front-End THA
For gigahertz sampling rate operation, it is preferred to have a front-end THA as it can improve the dynamic performance of an ADC. By holding the analog sample static during digitization, the THA largely removes errors caused by skews in clock delivery to a large number of comparators, signal-dependent nonlinearity, and aperture jitter [7].
The designed THA takes the open-looped architecture, as it is presented in Figure 2. The bootstrapped switch is adopted as its equalized resistance has little to do with the input voltage, thus improving the THA’s linearity. Also, its overdrive voltage is larger than the normal MOS switch, so the equalized resistance is smaller, and the sampling rate can be improved.
As the designed THA should be working at 2 GSps while having a resolution of over 8 bits, a slave THA has been designed after the master THA, shown in Figure 2. The slave THA tracks and holds the signal of the master THA. As the input signal of slave THA is less varying than the original input signal, the linearity requirement of the slave stage is much easier to realize than the master stage. To gain a large bandwidth for the THA, the slave stage also takes the bootstrapped switch, but much easier than its master counterpart.
The simulation results demonstrate that the master-slave THA has a good performance. For clock of 2 GHz, its SNDR performance for different input signal frequency is shown in Figure 3. Simulation results demonstrate that the THA’s signal to noise and distortion ratio (SNDR) is better than 61.5 dB up until the Nyquist input frequency.
2.2. Folding and Interpolation Network
With the analog preprocessing, the F&I architecture can better balance the ADC’s area, power, and performance. The preamplifier array generates the original zero-crossing points, but they are never enough. As can be seen in Figure 1, the two-stage cascaded F&I was taken in this design with interstage SHA circuit in between. These two stages are similar so they can be discussed together. With the help of F&I network, enough zero-crossing point will be generated while the system area and power are much smaller than its flash counterpart.
The first key element in designing the folding circuit is that it should have enough bandwidth to make sure signal can be settled within the limited time especially for ultra-high-speed ADCs. Second, it should have a certain gain to suppress the offset of next stage. Third, its offset should be controlled within a limited amount.
Figure 4 is the proposed F&I network. is the input differential pair as the folding factor is 3. and have two roles, first to insulate the signal from the input. Second, as the drain of three MOSFET is connected, its output capacitance is very large. With small sized and , the bandwidth of the folding circuit can be increased. The AC simulation of the folding circuit is shown in Figure 5. The gain is 5.382 dB and its −3 dB bandwidth is close to 4.9 GHz, suited for the ADC.
2.3. The Spark Code Elimination and Latch Circuit
In the fine channel, the cycled thermometer code is produced after the comparator array and should be coded into the digital output. Like its flash counterpart, because of the process mismatch and comparator’s metastability, the continues 1s will have some 0s in between; this is called spark code or bubbles. The spark code will cause quantization error in ADCs, no matter what kind of coding it takes.
In [8], the merits and demerits of rom-coding and gray-coding are compared. According to its conclusion, the rom-coding is taken in this design. First the thermometer code should be translated into 1-of-n code, as the possibility of 2nd order spark code can be neglected as compared with the first-order spark code; usually the three-input AND gate will be used to eliminate the spark code. Also, before the rom-coding, a latch stage should be added. If not, there will be error as the delay of different modules can be different. For this design, 32 latches will be needed, and they will take up a lot of area and power dissipation.
To save area and power, a novel four-input AND gate is created instead of the three-input AND gate, shown in Figure 6. Its three inputs are the same as the three-input AND gate; the added fourth input is the clock signal to do the signal latch. Simulation results demonstrate that the four-input AND gate can eliminate the spark code and at the same time latch the signal while use less area and power.
2.4. The Foreground Calibration Circuit
With CMOS technology scaling down, it is possible to build faster and low power digital circuit. However, because of the lower supply voltage, smaller intrinsic gain, and serious transistor mismatch, analog circuit does not benefit as much as its digital counterpart. Thus using the digital circuit to improve the analog performance became more and more fascinating. Here the foreground digital assisted calibration is presented to calibrate the zero-crossing point error, thus improving the performance of the folding and interpolation ADC. Although the background calibration seems better because it will not interfere the main circuit, in this design foreground calibration is adopted. The reasons are listed in here: (1) the background calibration is much more complicated and it will take much more area and power consumption; (2) for the folding and interpolation ADC, its offset is not sensitive to the temperature change and environment. In [3], test results demonstrate that the INL of ADC hardly changed within 50 hours since being powered up. Also, in [9], the author demonstrate that, for 10-bit folding ADC, for temperature change from 0 to 100 degree, the SNDR change is only 0.9 dB. Figure 7 is the diagram of the proposed foreground digital assisted calibration circuit and its connection to the main circuit.
The calibration happened when it is powered up. The offset of the preamplifier, the folding, and interpolation network and the comparator array will be measured and stored in the DFF arrays. When the ADC goes into normal operation, the voltage stored in the DFF arrays will go through the DACs to be analog and compensate the ADC’s offset.
The calibration circuit contains following important modules:(1)The calibration clock generation circuit: it receives the calibration trigger and controls the whole calibration process. The key point for the circuit is that the generated 16 calibration pulses should not have any overlap.(2)The 5-bit counter: it can add or subtract according to the comparator results to get the correct digital offset code. It is the core of the calibration circuit.(3)The DFF array: the DFF array can be used to store the offset voltage in digital form. As one channel of preamp calibration needs five DFFs, as mentioned above, there are 16 channels which need to be calibrated, so altogether there are 80 DFFs used in here.(4)The digital-to-analog converters (DACs): the DACs are used to translate the stored digital form offset into analog and compensate for the actual offset of the ADC. Here, the simple binary current DAC is adopted to reduce power and area.
In the simulation, one of the sixteen preamps’ differential channels were made to be different. From Figure 8 it can be seen that the channel goes into calibration in 250 ns. Because of the mismatch, at first the differential output of the preamplifier is larger than 150 mV, when the calibration ended, the output approaches zero, and the output of the comparator changes between 0s and 1s. The stored offset in this DFF array is between 10101 and 10110, shown in Figure 9. The simulation results demonstrate that the calibration circuit works all right.
3. Layout and Simulation Results of the ADC
The ADC is designed in TSMC 90 nm CMOS technology. The layout is presented in Figure 10. Its area is 930 μm 930 μm. For the sampling rate of 2 GSps, Nyquist input signal frequency, the FFT results show that the effective number of bits (ENOB) is 7.338 bit, presented in Figure 11. For input signal frequency smaller than 1 GHz, the SNDR is better than 45.93 dB, which shows that the ADC has a good dynamic performance.
The ADC’s performance and comparison with other published ones are presented in Table 1.
4. Conclusions
In this paper, a single channel 2 GSps, 8-bit F&I ADC with foreground calibration in TSMC 90 nm CMOS technology is presented. The ADC utilizes cascaded folding, with foreground digital assisted calibration to correct the error of zero-crossing point caused by the circuit offset. Chip area of the whole ADC including pads is 930 μm × 930 μm. Postsimulation results demonstrate that, under a single supply of 1.2 volts, the power consumption is 210 mW. For the sampling rate of 2 GSps, the SNDR is 45.93 dB for Nyquist input.
Competing Interests
The authors declare that there is no conflict of interests regarding the publication of this paper.
Acknowledgments
The research was supported by Scientific Research Foundation of Nanjing University of Posts and Telecommunications (NUPTSF Grants no. NY213076 and no. NY215138) and Open Project of State Key Laboratory of Millimeter Waves, Southeast University (no. K201727).