Research Article  Open Access
Wael Dghais, Malek Souilem, Fakhreddine Zayer, Abdelkader Chaari, "Power Supply and TemperatureAware I/O Buffer Model for SignalPower Integrity Simulation", Mathematical Problems in Engineering, vol. 2018, Article ID 1356538, 9 pages, 2018. https://doi.org/10.1155/2018/1356538
Power Supply and TemperatureAware I/O Buffer Model for SignalPower Integrity Simulation
Abstract
This paper presents the development and evaluation of a largesignal equivalent circuit model that accounts for the power supply fluctuation and temperature variation of I/O buffers circuit designed based on the fully depleted silicon on insulator (FDSOI) 28 nm process for signalpower integrity (SPI) simulation. A solid electrical analysis based on the working mechanisms of the nominal I/O buffer information specification (IBIS) like model is presented to support the derivation of an accurate and computationally efficient behavioral model that captures the essential effects of the power supply bouncing under temperature variation. The formulation and extraction of the Lagrange interpolating polynomial are investigated to extend the nominal equivalent circuit model. The generated behavioral model is implemented using the NewtonNeville’s formula and validated in simultaneous switching output buffers (SSO) scenario under temperature variation. The numerical results show a good prediction accuracy of the time domain voltage and current waveforms as well as the eye diagram of the highspeed communication I/O link while speedingup the transient simulation compared to the transistor level model.
1. Introduction
Signal and power integrity (SPI) assessment of highspeed digital communication inputoutput (I/O) links is important for the design analysis and verification of modern memory and chiptochip interfaces in order to figure out SPI problems at an early design stage [1–11]. The highspeed I/O link design has to also comply with certain specifications regarding the process, supply voltage, and temperature variation to obtain the target performance [12–16]. In fact, the temperature and power supply variations not only reduce the noise margins of digital circuits but also change the nanoscale output buffer/driver’s operating point and dynamics [4, 5, 9, 10, 14]. The I/O link is composed by an active nonlinear part representing the I/O buffers that bond the die to the passive package and the printed circuit board (PCB) interconnects in order to ensure reliable highspeed digital data communication between the integrated circuits (ICs) I/O ports of the DDR memory and CPU, as depicted in Figure 1. Since, I/O buffers are designed based on transistors, they are characterized by a nonlinear dynamic behavior which is usually the main cause of signal distortions under high data rate transmission (i.e., short rise and fall time) and simultaneous switching output (SSO) buffers which generate the bouncing of the onchip supply and ground voltages (e.g., simultaneous switching noise (SSN)) [1, 5, 8].
The SPI assessment is carried out by means of transient simulation in order to consider the interaction between the nonlinear dynamic output impedance of the semiconductor devices (i.e., I/O buffers) with the linear dynamic effect of the RLC package and the PCB traces. Transistor level (TL) models of the I/O buffers are impractical to use for evaluating the electrical performance of the highspeed digital I/O link because they reveal the detailed TL information about the design’s process and their transient simulation is timeconsuming in the electronic design automation (EDA) tools, [2–6, 15, 16]. Besides, the manufacturers are often reluctant to release SPICE TL models for general use [7–11]. Therefore, the effective behavioral modelling of I/O buffers is an appealing alternative that hides the intellectual property (IP) of the I/O buffer’s circuit and enables a fast and accurate SPI transient simulation of the highspeed communication I/O links, [1–16].
Recently, poweraware I/O buffer models were proposed by enhancing the nonlinear parametric and surrogate modelling approaches, [4–9] for SPI analysis. The parametric behavioral modelling algorithm proposed in [5] and the modified equivalent circuit and tablebased I/O buffer information specification (IBIS) like model presented in [9] are valid only for a designed I/O buffer physical structure where the predriver logic and the driver’s last stage are powered by separate supply and ground voltages (e.g., ). This assumption limits the validity of the proposed modelling solution and requires an a priori knowledge of the I/O device physical structure which may be difficult to access due to IP issues. Besides, the parametric models rely on the use of curve fitting techniques and nonlinear optimization algorithms (e.g., Levenberg–Marquardt) for parameters identification during the training phase [3–6, 17, 18]. They differ from the nonlinear physicsbased and industry standard IBIS modelling algorithm in the model’s formulation, extraction, and implementation steps [7–10]. Moreover, both modelling approaches cannot directly simulate continuous temperature variation because they rely only on the use of discrete process–supply voltage–temperature data [4, 7].
This paper proposes an extended equivalent circuit behavioral model which simultaneously considers the signal and power integrity domains and allows the incorporation of temperature variation. A general behavioral modelling framework based on the generation procedure of a nonlinear dynamic I/O buffer IBISlike model is described while disregarding any assumption on the powering techniques (i.e., supply and ground voltages) used in the I/O buffer circuit structure. In fact, the predriver and the driver’s last stage can be connected to the same power supply; therefore, the SSN affects both the predriver and driver’s last stage circuits. In fact, the analysis based on the nonlinear electrical and physical mechanisms of the I/O buffers enables the effective integration of the power supply voltage fluctuation and continuous temperature variation in the equivalent circuit IBISlike model’s functions. Accordingly, the interpolated model is derived, based on Lagrange polynomial representation, to explicitly incorporate the power supply port’s voltage and temperature variables. The accuracy and computational efficiency of the extended model formulation are ensured by numerically implementing the interpolating polynomials as NewtonNeville’s representations.
The rest of this paper is organized as follows. Section 2 details the mathematical model structure derivation and analysis in order to effectively include both the continuous power supply fluctuation and the temperature variation through Lagrange polynomial interpolation. Section 3 presents the model implementation and numerical validation results. Finally, conclusions are drawn in Section 4.
2. Model Derivation and Extraction
2.1. PowerAware Model
At the nominal power, , and ground, , supply voltage values, the nominal model relating the driver’s output current, , to the voltage controlling variables is where and represent the pullup (PU) and pulldown (PD) currents, respectively. The gate voltage controls the activation of the PU and PD transistors according to the bit sequence transmitted by the logic core, . stands for the time derivative dependence of the output currents and on the input voltage electrical variables and , as presented in Figure 2.
As SSO occurs, the large voltage bouncing of the onchip, , affects the input controlling voltage differences of the PMOS transistors, for instance, . This gate–source modulation effect [9], in which the nominal IBIS model fails to predict, changes the operation regions of the PU and PD transistors network (i.e., from saturation to linear and vice versa) of the driver’s last stage and also of the predriver’s stage logic if they are powered by the same power/ground supply voltages, as shown in Figure 2 [5–9]. It is worth noting that continues fluctuating even after the input voltage, , reaches the steady states. In order to develop a model coupled with observable electrical variables, which provides reassurance in validating the model for packaged devices, the mathematical formulation of the extended twopiece IBISlike model is derived based on the interpolation of multidimensional function (2). It captures the gate modulation effect to accurately predict the current and voltage waveforms at the power and ground nodes [2, 9]:where , , , and . and are nonlinear dynamic functions describing the driver’s last stage largesignal output admittances of when its input, , is kept at high (‘’) or low (‘’) logic states, respectively. and functions can be parameterized by means of spline functions with finite time differences [2], rational function [3], and artificial neural networks [5, 6, 18, 19]. Then, they are fitted with the acquired inputoutput transient voltage and current when the output voltage excitation is connected between the poweroutput port and groundoutput port [3–6]. Another approach consists in postulating the model as a physicsbased nonlinear equivalent circuit model (3) [7–9]. This nonlinear currentcharge (IQ) output admittance model for the PU and PD driver’s last stage extends the standard IBIS model and can be implemented as lookup tables (LUTs). where function models the singleinput single output (SISO) conduction output currentvoltage (IV) relationship and captures the displacement current modelled as a SISO capacitancevoltage (CV) relationship [7–9] for the PU and PD devices under supply voltages variation. The singlevalued and functions can be extracted from pulsed time domain measurements [10] or from biasdependent scattering (S) parameters measurements [20], when the excitation voltages are connected between the power/ground and output nodes. These nonlinear capacitances capture the nonlinear delay of the power supply signals propagating from power node till the output port during and after the switching activities of the input port (e.g., after the input signal rising and the falling edges).
Once the functions modelling the driver’s last stage PU and PD admittances are extracted, the step input describing functions (SDFs), and , that describe the input port (i.e., predriver) nonlinear switching characteristics under input rising transition (i.e., bit pattern ‘01’) and falling transition (i.e., bit pattern ‘10’) are extracted by means of a linear inversion [2–9]. The single extracted SDFs, at the nominal power supply voltage, , is capable of accurately predicting the predriver’s analog switching when it is powered by a separate supply voltage from the driver’s last stage because the SSN will not affect the predriver’s operation and its electrical characteristics [4–9].
Since the IBIS nominal model relies on the use of a fixed SISO IV functions with a linear output capacitance under a fixed low and high dc states of the input voltage (i.e., or ), the SPI modelling task consists of including the gate modulation effects in the IBIS model formulation. For instance, the doubleinput single output (DISO) IV surface characteristics of the PU and PD networks can be approximated as a multiplication of two SISO nonlinear functions for an NMOS FDSOI transistor, for instance, as where is the saturation current defined for an NMOS transistor as . The nonlinear transfer characteristic of the transistor is defined as The transistor output characteristic is defined as . The extraction of the static and is detailed in [9]. The contribution of the extended IBISlike power supplyaware model consists of proposing an interpolating based technique that approximates the gate modulation nonlinear static, , and dynamic effects on both the predriver and driver’s last stage. For instance, the nonlinear largesignal transfer characteristic vs of the predriver’s stage, shown in Figure 3, can be approximated or interpolated by a second or higherorder polynomial expansion for the accurate prediction of the new SDFs according to the change of the onchip (i.e., gate modulation effect). However, the adequate selection of the polynomial order should be investigated in order to find the best compromise between the developed model’s accuracy and computational cost.
Since the gate voltage is not accessible (i.e., not observable), the static effect of variation on the SDFs is captured by sweeping the value of in order to account for large power supply variation aside from the nominal value. Therefore, the additional SDFs which are extracted, from the transient TL simulation, for different dc power supply, , are interpolated by means of the Lagrange polynomial. Accordingly, the new scaling coefficient of SDFs is computed during the transient simulation of the driver’s circuit. where stands for the extracted SDFs that capture the predriver’s switching dynamics for different values of the power supply . is the Lagrange polynomial order which is chosen such that
The Lagrange interpolation (5) leads to a nonlinear model which is explicit in for the PU and PD devices. It is used to predict the SDFs functions that emulate the gate voltage modulation under SSO. However, the a priori decided polynomial degree affects the number of required SDFs that increase the characterization and identification times while increasing the memory space and running complexity of the proposed model. Furthermore, the sampling points of the Lagrange interpolating polynomial are taken according to predriver’s conductance function nonlinearity and Chebyshev nodes in order to avoid oscillation and obtain a good interpolation accuracy with a low polynomial order [15, 16].
2.2. TemperatureAware Model
In order to efficiently integrate the temperature variation in the power supplyaware driver’s model, the dependence of the threshold voltage, , on the temperature is extracted, based on the dc simulation data of the TL model, though the second derivative of the short channel FDSOI transfer characteristics, , as shown in Figure 4 [21, 22]. The determination of the dependence of the saturation current, , [12, 14], on the temperature is shown in Figure 5. is the maximum “ON” current determined when the PU and PD transistors work in the saturation region. For instance, is the current value defined when and for an NMOS transistor [12, 14]. Obviously, the second derivative method cannot be directly applied without digital preprocessing of the acquired measurement noisy data. Since the derivative amplifies the noise, this method [21, 22] becomes impractical and fails in identifying the exact threshold voltage. As shown in Figure 5, the temperature variation linearly affects and nonlinearly affects [12, 14, 20, 21].
(a)
(b)
Therefore, a nonlinear interpolating model should be derived in order to capture these effects and incorporate them in the nominal power supplyaware model which is formed by the IQ model for the driver’s last stage and the SDFs timing functions capturing the predriver’s stage nonlinear dynamics. Consequently, the Lagrange interpolating polynomials is used to accurately approximate the nonlinear dynamic effects of the temperature variation on the predriver’s SDFs (7) and the driver’s last stage PU and PD IV and CV functions (8). where stands for the extracted SDFs for different values of the temperature . is the order interpolating Lagrange polynomial. where represents the extracted and nonlinear functions of the driver’s last stage for different values of the temperature . is the Lagrange polynomial that captures the dependence of the driver’s last stage nominal output admittance on the temperature variation.
3. Validation of Model’s Extraction and Implementation
3.1. Model Extraction Results
Several Lagrange polynomial orders have been tried to interpolate the proposed nominal IBISlike model in order to capture the power supply and temperature variations. Considering the analysis and the observation of nonlinearity of the previous sections and, taking into account the computational running complexity of the generated behavioral model, the thirdorder (e.g., ) Lagrange polynomial is selected for the power supplyaware model. The prediction accuracy of the interpolated SISO IV characteristic by a cubic Lagrange polynomial to predict the DISO IV characteristic (i.e., gate modulation effect) at the nominal temperature is compared with the dc simulation of the driver’s TL model as shown in Figure 6. Moreover, the interpolation accuracy of the thirdorder Lagrange polynomial of the extracted function is shown in Figure 7. The PU nonlinear capacitance, , seen between the poweroutput port, is extracted from biasdependent scattering Sparameters [20], when the excitation signal is now connected between the power supply and output nodes [4–6]. The good prediction of the interpolated singlevalued SISO IV and CV relationships confirms that the cubic Lagrange polynomial is an adequate choice for including the effect of the PU and PD transistor’s turnon at the subthreshold voltage region. Similarly, the effects of the temperature variation on the behavioral model functions, and , are properly incorporated through the cubic Lagrange polynomial.
Although the secondorder Lagrange interpolating polynomial is more practical to use with the IBIS specification that already provides the (min, typ, max) data for capturing the effect of continuous and dynamic variations of the temperature and supply voltage variables, these IV and voltage time (Vt) data which are sampled at three temperature and supply voltage, , points have to cover the wide working range of the power supply voltage and temperature variables in order to avoid a large polynomial extrapolation error [14–16]. Moreover, it was tested that the fitting accuracy of the cubic interpolating Lagrange polynomial is better than the quadratic case in approximating the nonlinear relationship, versus , therefore capturing the temperature variation on the predriver’s stage (i.e., ) and driver’s last stage (i.e., ). For these reasons, additional Vt curves for and values have to be added to the IBIS specifications and library in order to enable higherorder Lagrange polynomial interpolation for the accurate power supply and temperatureaware model prediction [7, 15, 16].
3.2. Model Implementation and Validation
Besides accuracy, the model’s computational cost is an important factor to consider during the numerical model’s implementation step because real applications such as bus simulation require the transient simulation of many I/O devices [3–9]. The SISO IV and CV LUTs, seen between the poweroutput port and groundoutput port of the driver’s last stage, respectively, are required for the accurate prediction of bouncing. The extracted CV functions, and , are integrated to retrieve the chargevoltage (QV) for more computationally efficient IQ model implementation [10]. The polynomial implementation based on the Lagrange representation has a high number of floating points operation (FLOPs) (i.e., , ) which are required for additions and multiplications. Therefore, it would be better to construct and store the tabular function as Newton or Neville’s formula that speeds up the evaluation of the unique interpolating polynomial with FLOPs. Moreover, the addition of another sampled IV, QV, or SDFs for higherorder interpolation with respect to temperature and power supply variations, in the Newton construction, avoids the recalculation of the previous coefficients of the polynomials.
The implemented model architecture, using NewtonNeville’s formula that captures the effects of power supply bouncing and temperature variation, is shown in Figure 8. The validation circuit, shown in Figure 9, describes three drivers which are simultaneously switching. The SSO buffers lead to the fluctuation of the onchip power supply due to the package parasitic inductance and resistance .
The single driver is formed by four cascaded inverter stages with increasing driving capability designed based on CMOS FDSOI 28 nm technology from STMicroelectronics. Each output buffer drives a transmission line (, ) loaded by a parallel circuit composed of and . The required data used for the extraction of the model’s functions was recorded from the driver’s circuit simulations described by the TL model BSIMSOI in Cadence. The model was generated and implemented in the advanced design system (ADS) from Keysight Technologies. The normalized mean square error (NMSE) is used to quantify the prediction accuracy between the TL and proposed model’s signals: where signals and correspond to the voltage or current waveforms predicted by the TL model and the proposed power and temperatureaware behavioral model, respectively. The good agreement between the predicted and power supply signals, and , of the TL and the proposed interpolated models at the second driver, while all the output buffers are driven by the bit pattern “01100101010” at 800 Mbps speed and equal rise/fall time of 0.1 ns, is shown in Figures 10 and 11, respectively.
The maximum timing error of the rising, , (e.g., L to H) and falling, , (e.g., H to L) transitions are presented in Table 1 in order to quantify the accuracy of the output switching transitions at the RC parallel circuit which emulates the receiver’s impedance of the highspeed digital communication I/O link. For instance, the MTE of waveform at the rising and down transitions are about and , respectively, at the temperature values °C and °C.

An improved modelling accuracy can be achieved by using higher interpolating points with respect to the power supply, , and temperature which lead to a longer identification (e.g., characterization) time along with more data for storing the interpolating SDFs and IQ functions in the EDA tools which consequently affects the model’s computational cost. While the signal prediction of the proposed model in Figures 10 and 11 is not as accurate as the nominal twoport model which is used only for the signal integrity assessment, the selected interpolating (i.e., sampling) points (e.g., ) are minimized in order to alleviate the running computational complexity without sacrificing the accuracy of the extended IBISlike model in predicting the SPI propagating signals at the I/O and power terminals at different temperature values. In fact, the extension of the twoport IBISlike model to capture the power supply and the temperature effects is optimized in order to balance the tradeoff between the model’s accuracy along with the identification time and running complexities.
Furthermore, the eye diagram prediction of the signal after the transient simulation of the setup described in Figure 9, where the three drivers described by the TL and the proposed IBISlike driver’s models simultaneously transmit a random 1024bit stream at the temperature 20°C, 60°C, and 120°C, is depicted in Figure 12 where the eye opening parameters, the width, , and the height, , are also defined. As seen, the proposed power supply and temperatureaware model accurately predicts the inputoutput distortion effects under SSO and temperature variation when compared with the TL response. The achieved accuracy and model simulation efficiency using an i7 PC at 2.4 GHz, with 8 GB of RAM, are compared in Table 2. The computation time is estimated as the mean of the total stopwatch times of the transient simulator.

The prediction accuracy of the eye diagram is quantified by comparing the eye opening parameters for different temperatures as presented in Table 3.

The relative error between the TL and the proposed behavioral model of the eye width, , is about 6.49%, 2.44%, and 3.23% while the relative error of eye height, , is about 8.00%, 10.28%, and 5.93% at , , and , respectively. Accordingly, the proposed behavioral model is accurate in predicting the eye opening parameters with an error less than 6.5% in the eye width and an error less than 10.28% in the eye height at different temperature values. The prediction error can be reduced by selecting more sampling points while generating the power and temperatureaware models. Therefore, additional nonlinear IQ functions and SDFs need to be stored in the EDA library and a higher polynomial order is required for performing the interpolation which will affect the simulation time.
4. Conclusions
This paper has presented the generation of a power supplyaware I/O buffers model accounting for temperature variation in order to enhance the SPI simulation capabilities of the nonlinear equivalent circuit IBISlike model. The extended model accurately predicts the coupling of the SSN in data signals while considering temperature variation. The model’s numerical implementation (i.e., FLOPs) was optimized by means of Newton construction of the interpolated thirdorder polynomials of the LUTs IV, QV, and SDFs functions implementation. The accuracy and the computational efficiency of the proposed solution were verified and quantified and a significant speedup of 6× of the simulation time is achieved in predicting the eye diagram of the highspeed communication I/O link.
Data Availability
The data used to support the findings of this study are available from the corresponding author upon request.
Conflicts of Interest
The authors declare that they have no conflicts of interest.
Acknowledgments
The authors acknowledge STMicroelectronics and Circuit Multiproject (CMP) for providing the CMOS28FDSOI design kit.
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Copyright
Copyright © 2018 Wael Dghais et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.