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The Scientific World Journal
Volume 2014 (2014), Article ID 580385, 6 pages
Research Article

Designing a Ring-VCO for RFID Transponders in 0.18 m CMOS Process

1Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, 43600 UKM, Bangi, Selangor, Malaysia
2School of Electrical and Electronics Engineering, Chung-Ang University, Seoul 156-756, Republic of Korea

Received 27 September 2013; Accepted 30 October 2013; Published 22 January 2014

Academic Editors: A. García-Zambrana, A. Jugessur, and A. Srivastava

Copyright © 2014 Jubayer Jalil et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


In radio frequency identification (RFID) systems, performance degradation of phase locked loops (PLLs) mainly occurs due to high phase noise of voltage-controlled oscillators (VCOs). This paper proposes a low power, low phase noise ring-VCO developed for 2.42 GHz operated active RFID transponders compatible with IEEE 802.11 b/g, Bluetooth, and Zigbee protocols. For ease of integration and implementation of the module in tiny die area, a novel pseudodifferential delay cell based 3-stage ring oscillator has been introduced to fabricate the ring-VCO. In CMOS technology, 0.18 m process is adopted for designing the circuit with 1.5 V power supply. The postlayout simulated results show that the proposed oscillator works in the tuning range of 0.5–2.54 GHz and dissipates 2.47 mW of power. It exhibits a phase noise of −126.62 dBc/Hz at 25 MHz offset from 2.42 GHz carrier frequency.

1. Introduction

The operating frequency ranges of current RFID systems established for international standards extend from 135 kHz to 2.45 GHz in applications of biomedical, supply chain, public transport, and many more areas [1, 2]. Despite its emergence in today’s world, RFID deployment in numerous applications is a key challenge for technologist due to multiple standardization issues and expensive vendor-specific readers. Moreover, RFID transponders (also known as tags) operated in several bands—high frequency (HF) (13.56 MHz), ultra-high frequency (UHF) (860–915 MHz), and microwave band (2.4 GHz)—have limited operational range to cover less than 2 m to maximum 9 m [3]. To overcome these shortcomings, the concept of readerless RFID system based on IEEE 802.11 b (Wi-Fi technology) and IEEE 802.15.4 (Zigbee) compliant standards has been proposed in [4, 5], respectively. In these systems, implemented RFID transponders are battery-powered active devices and their operating frequency is 2.4 GHz (unlicensed ISM band). Effective use of the active transponder’s power is undoubtedly a crucial concern to implement in these RFID systems.

Analog transceiver in gigahertz range RFID transponder dissipates substantial amount of power during communication. In the RF transceiver, one of the key blocks is the frequency synthesizer or local oscillator. The phase locked loop (PLL) based frequency synthesizer is very popular in RF application from the outset. A PLL is a combination of phase detector (PD), low pass filter (LPF), voltage-controlled oscillator (VCO), and frequency divider. In a PLL, the most power hungry module is VCO which generates frequency and changes the oscillating frequency by varying control voltage. Nowadays, high frequency VCOs are built on complementary metal oxide semiconductor (CMOS), BiCMOS, SiGe, InP, and GaAs technologies for various ranges of frequencies. In comparison with other technologies, CMOS dominates the semiconductor industry nearly three decades due to its rapid evolution, continual downscaling of process, lower power dissipation, and reduced cost of fabrication [69]. Until now, LC-type and RC-type of CMOS VCOs have been used in wireless communication systems [10]. Typically, a VCO performance is analyzed by low phase noise, low power consumption, low voltage operation, high-speed oscillation, multiphase application, supply sensitivity reduction, simplified integration method, small layout area, and wide tuning range. So far, LC-based VCO has low level of phase noise among all VCOs. However, it has narrow tuning range, greater power consumption, and large die area [11]. In addition, it is very difficult to integrate inductor in digital CMOS technology. These limitations on LC-VCO can easily be overcome by ring-VCO.

This research work focuses on designing a low power pseudodifferential (PD) delay cell based ring-VCO with improved phase noise performance, which is suitable for high data rate active RFID transponder compatible with Wi-Fi, Bluetooth, and Zigbee networks. The architecture and operation of the proposed VCO will be presented in Section 2. The designing of the PD delay cell of the VCO will be described in Section 3. Finally, the postlayout simulation results will be discussed and compared in Section 4, followed by conclusion.

2. Three-Stage Ring-VCO Architecture

In general, a number of delay cells, which are connected in a positive or regenerative feedback loop for building a basic ring oscillator (RO), are the main basis of ring-VCO. Unlike LC, the on-chip RO is an inductor-free circuit and it is built by delay stages without a frequency selective network (resonant circuit). These delay stages or delay cells are inverting amplifiers. A common practice of ring-VCO implementation in CMOS process is accomplished by either single-ended or differential topology of delay cell. The single-ended ring topology comprises inverters and each inverter is made up of an NMOS and PMOS transistors. On the other hand, a differential topology includes a load (active or passive) with an NMOS differential pair. Currently, differential circuit topology is getting acceptance among designers as it has common-mode rejection of supply and substrate noise [17]. Moreover, it could be formed by odd or even number of stages and is possible to achieve both in-phase and quadrature outputs in DROs [18].

Choosing optimum number of stages for construction of high frequency oscillator is an important part of designing ring-VCO. Two, three, and four stages are common structures for the development of DRO in wireless communication systems. Several novel delay cells have been demonstrated to compose the two-stage ring-VCO, but extra power is inevitably needed to provide an excess phase shift for oscillation satisfying Barkhausen criterion. On the other hand, implementation of 4 stages of RO consumes considerable amount of power due to additional stages. Though 3-stage ring oscillator cannot produce quadrature outputs like 2-stage or 4-stage RO, it is faster than its 4-stage counterpart. Moreover, in 3-stage RO, fulfillment of proper start-up conditions can easily be attained unlike even number ROs, where latch-up frequently occurs. Thus, for designing the proposed VCO, the 3-stage RO is chosen to increase the oscillation and to reduce power consumption concurrently.

For incorporation of 3-stage, single delay loop ring oscillator, only three of differential amplifiers are connected in a single delay path formation as shown in Figure 1. Dual delay loop, a technique for achieving maximum frequency levels, is not considered due to additional transistors and power consumption. Principle operation of the proposed oscillator structure is that if one of the nodes is excited, the pulse propagates through all the stages and reverses the polarity of the initially excited node. To explain the basic working principle of the DRO, let us consider a three-stage DRO , in which at time , the output of the first stage, voltage changes to logic 1 (denoted by edge ) as shown in signal waveform in Figure 2. When this logic 1 propagates to the end, it creates a logic 1 at the third stage, which, when fed back to the input of the first stage, creates a logic 0 in the first stage output denoting edge . When this logic 0 is propagated again through the loop, it toggles the output voltage of the first stage and trigger edge . For every single cycle, there are a downward and an upward transition, and the intrinsic propagation delay times of each delay cell, high-to-low and low-to-high , are associated with these transitions. Nevertheless, and could be equal or not depending on the specific delay cell configurations, and so the average propagation delay can be implied by the arithmetic mean of transition times, .

Figure 1: Block diagram of the 3-stage ring-VCO.
Figure 2: Corresponding waveform of the 3-stage ring-VCO and total period calculation.

For start-up and oscillation criteria, the transfer function for this ring oscillator with the number of stages set to three can be represented as where denotes voltage gain of each delay cell and denotes 3 dB bandwidth at each stage.

One of the criteria for oscillation is the phase shift of 180°; that is, each stage contributes with 60° of phase shift for three-stage RO, and the frequency at which it occurs is given as

The other criterion for oscillation is the loop gain (at ) which must be greater than 1 to achieve the minimum voltage gain per stage. Consider

By inserting the oscillation frequency expression of (2) into the gain equation (3), we can calculate the minimum voltage gain per delay cell:

For every signal cycle, there is a downward as well as an upward transition. Since the high-to-low and low-to-high propagation delays associated with these transitions are not usually equal, the average propagation delay is given by

A propagating signal has to pass twice through the chain of delay cells, for a total delay of , to complete one period. The oscillation frequency for an -stage ring is derived from the average propagation delay of the inverter. The frequency of the oscillation is expressed as

3. Design of Proposed Delay Cell Architecture

In this research, a pseudodifferential (PD) configured delay cell architecture for the ring-VCO has been introduced as shown in Figure 3. Due to the tail current source in true differential amplifier, the common-mode gain is reduced by increasing the output resistance of the bias current source. Conversely, the absence of tail current source in PD amplifier results in a large common-mode gain [19]. Moreover, since PD cell alleviates necessity of tail current transistor, it is free from flicker noise [11]. Additionally, it avoids redundant bias circuit which occupies a large space in integrated circuit (IC).

Figure 3: Schematic diagram of the proposed delay cell.

According to Figure 3, a pair of CMOS differential push-pull inverter is used as inputs in the new delay cell architecture. This input pair can be stated as complementary input pair. Each complementary input consists of two different sizing of PMOS and NMOS transistors. Additionally, two cross-coupled NMOS transistors are connected in parallel with input NMOS transistors. These cross-coupled NMOS transistors are introduced for fast switching speed. Sizes of all four NMOS in the cell are chosen unequally as well. In addition, a serially connected load capacitor with cross-coupled NMOS is employed in parallel with each NMOS input. Here, frequency tuning is achieved through a PMOS transistor connected directly with supply voltage.

The operation of the delay cell can be illustrated considering half-cell circuit. According to Figure 3, while the input In becomes high (near VDD), the input In becomes low (equal to zero volt). This occurrence turns on NMOS of the node In. In addition, cross-coupled NMOS is turned on due to close of PMOS at the input node In. On the other hand, PMOS of the input node In remains off. Then, voltage of the output node Out is grounded. During that period, charge from the capacitor , which is serially connected with , is discharged; or in other words, a path is formed, which sinks current from Out to bring its potential to 0 V. Similarly, if the input In turns into 0 (zero) V, then the input In becomes high (near VDD). Now, zero potential of the input In turns on PMOS and turns off NMOS , simultaneously. A cross-coupled NMOS , connected in parallel with the input NMOS , remains switched on till the complete discharge of capacitor of the other half circuit of this cell because potential of the output node Out becomes near VDD and turns on NMSO . Now, the previously discharged capacitor recharges again through . Here, a PMOS tuning transistor controls both charging and discharging operations of the load capacitor and eventually the frequency of the oscillator varies.

To calculate the operating frequency of the ring oscillator, a half circuit of the proposed delay cell in Figure 4 is considered. The transfer function of the delay cell is shown as follows: where is the transconductance of the transistor, is the total capacitance at the output node and is the resistance load due to channel length modulation. Calculation of the operating frequency is derived as follows:

Figure 4: Small-signal equivalent circuit of the half circuit of the delay cell for frequency analysis.

4. Results and Comparisons

The proposed delay cell circuit has been verified by using the EldoRF simulator (Mentor Graphics). The process parameters for the transistors used in this work correspond to Collaborative Micro-electronic Design Excellence Centre (CEDEC) 0.18 m standard 1P6 M CMOS technology. To determine the operating frequency of the proposed delay cell circuit, the postlayout simulated output frequency of the ring-VCO is shown in Figure 5. Frequency of 2.42 GHz is achieved, while the control voltage is set to 0.1 V. To obtain this result, the supply voltage is set to 1.5 V and 0.1 pF of each load capacitor selected in the circuit. The proposed circuit arrangement and different sizes of the transistors make it possible to get the required frequency. The operating temperature of the circuit is set to 27°C.

Figure 5: Simulated output of the proposed ring-VCO.

In order to validate the proposed circuit in wide frequency range, the simulation is done at different control voltages. A frequency tuning range of 80% is attained from 0.5 GHz to 2.54 GHz applying 0.8 V to 0 (zero) V as shown in Figure 6. In the proposed architecture, it is observed in Figure 6 that a linear relationship has been established between control voltage and frequency of oscillation.

Figure 6: Tuning range of the proposed ring-VCO at 27°C.

Since IEEE 802.11 b protocol is required to generate frequency from 2.412 GHz to 2.484 GHz, the proposed delay circuit makes the ring-VCO working on this frequency range, which is certainly a key parameter of readerless, active RFID transponder. All major short range as well as long range communication standards, for example, GSM, DCS-1800, WLAN IEEE 802.11 b/g, IEEE 802.11 FH (Bluetooth), and Zigbee, operate in the frequency range of 0.8 GHz to 2.5 GHz, where the frequency range demands exceptional VCO performance. However, the VCO phase noise requirement of Wi-Fi is not relaxed than Bluetooth or Zigbee standards, rather stringent, as bit error rate (BER) of Wi-Fi is much higher. For IEEE 802.11 b protocol, keeping BER better than 10−5, the phase noise must be met to −126 dBc/Hz at 25 MHz offset [20]. In our design, we have achieved single side-band phase noise of −126.62 dBc/Hz at 25 MHz offset from the carrier 2.42 GHz as shown in Figure 7. To generate 2.42 GHz frequency, 2.47 mW of power has dissipated this oscillator.

Figure 7: Single side-band (SSB) phase noise (PN) of the proposed ring-VCO.

The figure of merit (FOM) of the proposed ring-VCO can be calculated from the power dissipation and the phase noise of the simulated oscillation frequency by where is phase noise in offset frequency and is the frequency of oscillation of the ring-VCO. The achievable FOM is found to be −162.4 dBc/Hz. A layout of the chip is shown in Figure 8, where the VCO core occupies an area (without PADs) of 145 × 64 m2.

Figure 8: Layout of the pseudodifferential ring-VCO.

The principle of industry oriented EDA tools (such as Mentor Graphics, Cadence, etc.) is expected to have the closest simulation result to the experimental result. Here, we have used Mentor Graphics to design, simulate, and draw layout of our proposed design of VCO. Therefore, the postlayout simulation will be expected to agree with the actual measurement result after IC fabrication. The postlayout design (Figure 8) has been sent for fabrication using standard 0.18 m CMOS process including PADs and buffer circuit.

Table 1 summarizes the performance of our proposed ring-VCO along with other research works' results of ring-VCO for comparison. Compared to [15], this ring-VCO has better phase noise and high value of FOM at the expense of modest power. Its power consumption is significantly lower than [1214, 16]; and finally, its wide tuning range is notable than other reported works except that of [13].

Table 1: Performance comparisons of CMOS ring-VCO.

5. Conclusion

Despite the continuous improvement in the state of the art of VCOs in downscaling CMOS process, they still remain the most crucial blocks for high frequency PLLs. In this paper, a ring-VCO has been introduced for active, readerless RFID transponder compliant with established short-range communication networks, such as Wi-Fi, Bluetooth, and Zigbee. This proposed ring oscillator-based VCO is achieved by employing 3-stage delay cell, where each delay cell is configured as pseudodifferential circuit with complementary push-pull input. Wide tuning range and phase noise performance of the oscillator have been evaluated through postlayout simulation results. The comparison results show that the proposed ring-VCO’s comparable performances offer the benefit of operating in a low-voltage environment, reduced power dissipation, and tiny layout area. The proposed oscillator’s better phase noise performance is sufficient to achieve maximum data rate of 11 Mbps for Wi-Fi transceivers.

Conflict of Interests

The authors declare that there is no conflict of interests regarding the publication of this paper.


The authors would like to express sincere gratitude to the Ministry of Science, Technology and Innovation (MOSTI) for supporting this research project through its UKM-AP-ICT-20-2010 (Arus Perdana) program.


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