VLSI Design

VLSI Design / 2010 / Article

Research Article | Open Access

Volume 2010 |Article ID 639747 | https://doi.org/10.1155/2010/639747

P. K. Lala, A. Mathews, J. P. Parkerson, "An Approach for Implementing State Machines with Online Testability", VLSI Design, vol. 2010, Article ID 639747, 7 pages, 2010. https://doi.org/10.1155/2010/639747

An Approach for Implementing State Machines with Online Testability

Academic Editor: Rubin Parekhji
Received03 Jun 2009
Revised24 Dec 2009
Accepted09 Feb 2010
Published28 Apr 2010


During the last two decades, significant amount of research has been performed to simplify the detection of transient or soft errors in VLSI-based digital systems. This paper proposes an approach for implementing state machines that uses 2-hot code for state encoding. State machines designed using this approach allow online detection of soft errors in registers and output logic. The 2-hot code considerably reduces the number of required flip-flops and leads to relatively straightforward implementation of next state and output logic. A new way of designing output logic for online fault detection has also been presented.

1. Introduction

It is now widely accepted that transient errors are the major contributor of digital system failure [1โ€“6]. Several techniques have been proposed over the years for designing self-checking combinational circuits and state machines to cope with transient errors [7โ€“14]. An architecture for designing online/offline testable state machines was proposed in [11] that has an advantage over the traditional approaches to self-checking design. This method uses a 1-hot code to encode states, making the next state logic and output logic design straightforward. The disadvantage of the 1-hot code is that it requires n flip-flops to encode n states, which considerably increases the size of the circuit.

This paper proposes a technique for designing self-checking Mealy-type state machines whose registers and output logic are testable online. In a Mealy-type state machine the output is a function of the present state and current inputs [15]. The testable state machine uses a 2-hot code for state encoding instead of a 1-hot code used in [6]. The advantage of the 2-hot code over the 1-hot code is that it considerably reduces the number of flip-flops needed, while the next state and output logic are still relatively straightforward. Although it is possible to use an m-out-of-n code to encode the states of a state machine, an encoded state will have more 1โ€™s than the 2-hot code in cases where a circuit has more than ten states. As a result the next state logic will require more circuitry, thereby increasing the unreliability of the circuitry. A new method for designing the output logic is also proposed in this paper. This proposed design generates the output and the complement of the output using only transistors and buffers; this approach makes the resulting circuitry more hardware efficient compared to using multiple input logic gates and incurs less overhead than a conventional approach, for example, duplicate and compare [1].

2. Architecture for Online Testable State Machine

A top view of the architecture that can utilized to implement on-line testable state machines is shown in Figure 1; this is a modified version of that presented in [11]. The Output Logic takes in the present state and inputs, and generates the primary output ๐น and its complement ๐น ๎…ž simultaneously. ๐น and its complement can be compared externally to verify that they are the complement of each other. If they are not the complement of each other, there is a fault in the Output Logic.

As stated earlier in the proposed approach of state machine design, a 2-hot code is used to represent the states. A 2-hot code requires more flip-flops but simplifies the next state and output logic. Register ๐‘… represents the present state, and Register ๐‘„ , which feeds back into Register ๐‘… , represents the next state. Register ๐‘… and Register ๐‘„ have scan out features that allow them to be tested offline. The output of the next state logic is loaded into register ๐‘„ . The outputs of Registers ๐‘… and ๐‘„ are XORed and then compared by the Even Parity Checker. This determines if there is a transient error in the Next State Logic (details are discussed in the next section). The content of register ๐‘„ can also be scanned out to check for permanent fault(s) in the next state logic; this can be done offline.

3. Next State Logic Design

Using a 2-hot code, there are three possible relations between the present state and the next state. If two states have no 1โ€™s in common, they differ by four bits: State 1:โ€‰โ€‰ โ€‰1โ€‰1โ€‰0โ€‰0โ€‰0โ€‰0 State 2:โ€‰โ€‰ โ€‰0โ€‰0โ€‰1โ€‰0โ€‰1โ€‰0

If two states have one 1 in common, they differ by two bits: State 1:โ€‰โ€‰ โ€‰0โ€‰1โ€‰1โ€‰0โ€‰0โ€‰0 State 2:โ€‰โ€‰ โ€‰0โ€‰1โ€‰0โ€‰1โ€‰0โ€‰0

If two states have two 1โ€™s in common, they must be the same state.

Therefore, when using a 2-hot code, any two given states must have an even number of differing bits. In Figure 1, the XOR Module gives the number of differing bits between the present and next state, and the Even Parity Checker determines whether or not the XOR has an even number of 1โ€™s. If there is an even number of 1โ€™s in the XOR, then there should not be a single fault in either register nor in the Next State Logic. If there is a single fault in the Next State Logic or in one of the registers, the result may be a faulty 1 or a faulty 0 in the present state or next state. A faulty 1 or a faulty 0 in one of the registers would change the parity of the XOR function from even to odd. If there is an odd number of 1โ€™s in the XOR, then there is a fault in either the Next State Logic or in one of the registers, and it can be observed in the output โ€œNext State Check.โ€

Register ๐‘„ โ€™s values are set by the Next State Logic, using reset/preset on the flip-flops. The implementation of Register ๐‘„ is shown in Figure 2. All the flip-flops are reset to 0 on the rising edge of the system clock. After some delay, the Next State Logic sets the appropriate two flip-flops to 1 using preset (denoted by ๐‘ƒ in Figure 2). The Next State Logic should provide enough delay to ensure that the flip-flops have all been reset before the appropriate present state flip-flops are preset.

The Next State Logic may be implemented with only p -type transistors, as seen in Figure 3. One possible present state is when the ๐‘… 1 and ๐‘… 4 outputs of Register ๐‘… are 1. In the example in Figure 3, there are two inputs ( ๐‘‹ 0 and ๐‘‹ 1 ). If ๐‘‹ 0 = 0 and ๐‘‹ 1 = 0 , and both ๐‘… 1 and ๐‘… 4 are asserted, then a 1 is propagated to the outputs ๐‘ƒ 0 and ๐‘ƒ 1 , which denotes some particular state. This circuit may be repeated for all present states ( { ๐‘… 1 , ๐‘… 2 } , { ๐‘… 1 , ๐‘… 3 } , etc.).

4. Output Logic Design

The Output Logic must take in the present state and the inputs, and must generate the output and the bitwise inverse of the output, as seen in Figure 1. The goal here is to minimize the overhead required to generate F and F ๎…ž . Figure 4 shows the encoding scheme for four possible numbers of states and the transistor design that selects the appropriate state. A shared transistor is used for states that have a 1 in common. Since only one state can be active at a time, only one path can be active at a time, and this path gives the present state.

A similar approach, as shown in Figure 5, is used to design the portion of the circuit that gives the correct combination of inputs that are active.

In Figure 5, every possible input combination points to the corresponding path that is activated. Note that with three inputs there are eight possible input combinations and eight possible paths to be activated, in which one and only one path must be active at any given time. When Figures 4 and 5 are put together, the result gives us all possible combinations of present state and input combinations. Since only one path can be active in Figure 4 and only one path can be active in Figure 5, one and only one path will be active at any time when the two are put together. However, a difficulty arises in trying to connect the present state transistors with the input transistors (or connect Figures 4 and 5). For example, if state 1 is directly connected to inputs 1 and 2, and state 2 is directly connected to inputs 2 and 3 then state 1 will be connected to input 3, thus giving an incorrect value for F when state 1 and input 3 are activated. This can be avoided by using buffers to control flow of signals when multiple present state lines fan-in to a single input line. This technique will be illustrated using the following example.

Table 1 shows a transition table for a state machine and the resulting output equations. This state machine has six statesโ€”using all possible 2-hot combinations of the four state bits, two inputs ( ๐‘‹ 1 and ๐‘‹ 0 ), and two outputs ( ๐น 1 and ๐น 0 ).

Present stateInputsNext stateOutputs
R3R2R1R 0X1X0Q3Q2Q1Q0F1F 0









The output logic circuit for generating ๐น 1 and ๐น ๎…ž 1 from the example in Table 1 is shown in Figure 6; the inverters necessary to generate the complements of the inputs are not shown. This design combines the techniques shown in Figures 4 and 5 to give a path for any possible present state/input combinations that make ๐น 1 = 1 . For example, the transition table in Table 1 shows if ๐‘„ 3 โ‹… ๐‘„ 2 โ‹… ๐‘‹ 0 โ‹… ๐‘‹ 1 = 1 , then ๐น 1 = 1 . It can be seen in Figure 6, if ๐‘„ 3 โ‹… ๐‘„ 2 โ‹… ๐‘‹ 0 โ‹… ๐‘‹ 1 = 1 , then a 1 is propagated to ๐น 1 . At the same time, a 0 is propagated to not ( ๐น 1 ) in the bottom circuit through an equivalent path.

Notice that the right circuit is a replica of the left circuit, except (1) the p -type transistors are replaced by n -type transistors (2) all the input and state signals are inverted, and (3) the output has a pull-up mechanism instead of a pull-down mechanism. Because the circuits are alike, if a path is activated in the left circuit, then the same path must be activated in the right circuit. Since the left circuit propagates a 1 to the output or otherwise is pulled to 0, and the right circuit propagates a 0 to the output or otherwise is pulled to 1, the outputs will always be the complement of each other in the absence of a fault.

The buffers control the direction of signal flow in the circuit. They also act as amplifiers between multiple transistors connected in series. Since there is a resistance associated with all transistors, it is not desirable to have more than three transistors connected directly in series [16]. The more transistors in series the slower the circuit will be, although the transistors could be made larger than minimum to reduce the delay. In addition fewer transistors in series result in less resistance between the output and the power rails. A general rule of thumb as proposed in [17] is โ€œNo more than 4 n -channel or 3 p -channel devices in series in any gate.โ€

It should be noted that the number of buffers in Figure 6 may be reduced by configuring them in a different form. The buffers used in the pull-up circuit (Figure 6(a)) and the buffers used in the pull-down circuit (Figure 6(b)) are different. Figure 7 shows an implementation of these buffers.

The proposed technique has been applied to design a subset of MCNC of circuits selected as suggested in [18]. The results are listed in Table 2. The first column lists the number of transistors in the next state logic (NSL) of the benchmark circuits; similarly the second, third, and the fourth columns show the number of transistors required in the output logic (OL), XOR module (XOR), and parity checker (PAR) in each circuit. The total number of transistors is shown in the fifth column. The number of flip-flops includes Registers, those in register ๐‘… , Register ๐‘„ , and the Next State Checking logic of Figure 1.



It should be indicated that although different outputs in a multioutput circuit can share logic, sharing of logic between an output ( F ) and its complement ( F ๎…ž ) is not allowed in the proposed scheme so that a fault does not affect both output circuits at the same time thus preventing its detection. If there is a fault in one of these shared p -type transistors, the fault will be propagated to ๐น 0 and ๐น 1 , but not to ๐น ๎…ž 0 and ๐น ๎…ž 1 , therefore the fault will be detected. Similarly, a fault that appears in a shared n -type transistor will be propagated only to ๐น ๎…ž 0 and ๐น ๎…ž 1 but not to ๐น 0 or ๐น 1 and therefore will also be detected.

The transistor counts in the OL column in Table 2 were derived assuming no sharing of logic across different outputs. Thus the transistor counts may be reduced by possible sharing of logic. For example in Figure 5, output circuits ๐น 0 and ๐น 1 can share the p -type transistors that identify the present state by transmitting a 1. Similarly in Figure 6, the circuits that generate ( ๐น ๎…ž 0 ) and ( ๐น ๎…ž 1 ) can share the n-type transistors that identify the present state by transmitting a 0. However sharing could increase fan-outs in the circuits thereby requiring more buffers. Figure 8 shows a general layout of shared of transistors in a testable state machine designed using the proposed scheme.

5. Conclusion

This paper has proposed a method for designing state machines with online testability. The XOR Module and Parity Checker allow for online testing of Registers ๐‘… and ๐‘„ , and the Next State Logic. This design will detect any single stuck-at fault in the Next State Logic or in the Registers. The proposed technique uses a design approach that is different from that used for designing conventional CMOS-based design; it uses transistors and buffers rather than fully complementary transistors.


The first author was supported in part by the National Science Foundation USA under Grant 0925080.


  1. P. K. Lala, Self-Checking and Fault Tolerant Digital Design, Morgan-Kaufmann, Aberdeen, Scotland, 2001.
  2. C. Zhao and S. Dey, โ€œEvaluating and improving transient error tolerance of CMOS digital VLSI circuits,โ€ in Proceedings of the International Test Conference, pp. 1โ€“10, Santa Clara, Calif, USA, 2006. View at: Publisher Site | Google Scholar
  3. S. Mitra, N. Kee, and S. Kim, โ€œRobust system design with built-in soft-error resilience,โ€ IEEE Design and Test Computers, vol. 38, no. 2, pp. 43โ€“52, 2005. View at: Google Scholar
  4. M. Omana, G. Papasso, D. Rossi, and C. Metra, โ€œA model for transient fault propagation in combinatorial logic,โ€ in Proceedings of the 9th IEEE On-Line Testing Symposium (IOLTS '03), pp. 111โ€“115, July 2003. View at: Google Scholar
  5. K. Mohanram and N. A. Touba, โ€œCost-effective approach for reducing soft error failure rate in logic circuits,โ€ in Proceedings of the International Test Conference, pp. 893โ€“901, 2003. View at: Google Scholar
  6. F. Wang and V. D. Agrawal, โ€œSoft error rate determination for nanometer CMOS VLSI logic,โ€ in Proceedings of the 40th Annual Southeastern Symposium on System Theory, pp. 324โ€“328, New Orleans, La, USA, 2008. View at: Publisher Site | Google Scholar
  7. M. K. Stojฤev, G. Lj. Djordjeviฤ, and T. R. Stankoviฤ, โ€œImplementation of self-checking two-level combinational logic on FPGA and CPLD circuits,โ€ Microelectronics Reliability, vol. 44, no. 1, pp. 173โ€“178, 2004. View at: Publisher Site | Google Scholar
  8. G. L. Djordjeviฤ, M. K. Stojฤev, and T. R. Stankoviฤ, โ€œApproach to partially self-checking combinational circuits design,โ€ Microelectronics Journal, vol. 35, no. 12, pp. 945โ€“952, 2004. View at: Publisher Site | Google Scholar
  9. A. Matrosova and S. Ostanin, โ€œSelf-checking FSM design with observing only FSM outputs,โ€ in Proceedings of the 6th IEEE On-Line Testing Symposium (IOLTS '00), pp. 153โ€“154, Palma de Mallorca, Spain, 2000. View at: Google Scholar
  10. R. A. Parekhji, G. Venkatesh, and S. D. Sherlekar, โ€œA methodology for designing optimal self-checking sequential circuits,โ€ in Proceedings of the International Test Conference, pp. 283โ€“291, Nashville, Tenn, USA, October 1991. View at: Google Scholar
  11. P. K. Lala and A. Walker, โ€œA unified scheme for designing testable state machines,โ€ in Proceedings of the IEEE Asia Test Symposium, pp. 273โ€“278, Kyoto, Japan, 2001. View at: Google Scholar
  12. K. Mohanram, E. S. Sogomonyan, M. Gossel, and N. A. Touba, โ€œSynthesis of low-cost parity-based partially self-checking circuits,โ€ in Proceedings of the 9th IEEE On-Line Testing Symposium (IOLTS '03), pp. 35โ€“40, July 2003. View at: Google Scholar
  13. I. Levin, V. Ostrovsky, S. Ostanin, and M. Karpovsky, โ€œSelf-checking sequential circuitswith self-healing ability,โ€ in Proceedings of the 12th ACM Great Lake Symposium on VLSI, New York, NY, USA, April 2002. View at: Google Scholar
  14. B. Abramov, V. Ostrovsky, and I. Levin, โ€œDesigning self-checking circuits with smooth power dissipation,โ€ in Proceedings of the 24th IEEE Convention of Electrical and Electronics Engineers, pp. 1โ€“5, Eilat, Israel, 2006. View at: Publisher Site | Google Scholar
  15. P. K. Lala, Principles of Modern Digital Design, John Wiley & Sons, New York, NY, USA, 2008.
  16. J. M. Rabaey, A. Chandrakasan, and B. Nikokic, Digital Integrated Circuits, Pearson Education, Upper Saddle River, NJ, USA, 2003.
  17. M. Hoffman and J. K. Kim, โ€œDelay optimization of combinational static CMOS logic,โ€ in Proceedings of the 24th ACM Design Automation Conference, pp. 125โ€“131, 1987. View at: Google Scholar
  18. S. Yang, โ€œLogic synthesis and optimization benchmarks, user guide version 3.0.,โ€ in Proceedings of the International Workshop on Logic Synthesis, MCNC, Research Triangle Park, NC, USA, May 1991. View at: Google Scholar

Copyright © 2010 P. K. Lala et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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