A wide tuning band pass filter (BPF) with steep roll-off high rejection and low noise figure is presented. The design feature of steep roll-off high stopband rejection (>20 dB) and low noise figure (<6 dB) provides a wide tuning frequency span (1–2.04 GHz) to accept desirable signals and reject close interfering signals. The process variation aware design approach demonstrates robustness of the BPF after calibration from process variations, operating in 1.04 GHz tuning frequency span: almost zero deviation on center frequency, an average maximum deviation 1.16 dB on a nominal pass band gain of 55.6 dB, and an average maximum deviation 1.06 MHz on a nominal bandwidth of 12.3 MHz.

1. Introduction

When RF devices are upgraded to support future standards, IF amplifiers, mixers, band pass filters (BPFs), modulators, and demodulators are preferable to be tunable and cost-effective to meet different frequency band standards [1]. Reconfigurable RF minimizes duplicated RF front-end components and hence reduces energy and cost. Considering cognitive radio in the TV bands, there are narrow spectral holes between strong TV transmitter signals. To avoid blocking of the receiver, strong TV signals have to be rejected by tunable BPF of high linearity, high , and high stopband rejection. A typical example is for 10 MHz bandwidth in a wide tuning frequency range of 500 MHz in the TV bands. Reconfigurable RF devices include power amplifiers, antennas, band pass filters, and matching networks with high tuning speed and high linearity for reasons of size and cost.

Tunable BPF features include tunable frequency range, pass band gain, tuning center frequency span, bandwidth, noise figure, and stopband rejection. Several state-of-the-art CMOS design techniques such as gm-C filters, enhanced LC filters, N-path, and pseudo-N-path filters have been presented. Most of them have either low band pass gain, high noise figure, or low tuning frequency range [215]. The gm-C filters have the advantage of low power and high frequency. Their weak linearity is improved by applying linearization techniques such as resistive source degeneration, dynamic source degenerated differential pair, tunable feedback, and adaptive feedback. However, these techniques have low pass band gain and narrow tuning range [7, 10]. The -enhanced LC band pass filter through an adjustable negative-conductance generator is capable of operating in low-voltage supply but it has low pass band gain (−5 dB) and high noise figure (26.8 dB) [8]. Other -enhanced LC filter based designs were proposed in [9, 11]. The BPF in [9] consumes less power and has a tuning frequency range (400 MHz) with a pass band gain (23 dB). A low pass band distortion BPF proposed in [11] has a low pass band gain (0 dB). The high- integrated switched capacitor band pass filter [12] has a broad frequency band but a low pass band gain (−2 dB) and high power. A design using high- N-path band pass filter is proposed [13], which has a tuning frequency range (0.1–1 GHz) but low band pass gain (−2 dB). A novel inductorless tunable switched capacitor band pass filter based on N-path periodically time-variant circuit operates in a high frequency range (4–4.44 GHz) but has low pass band gain (−12 dB) and high noise figure (14 dB) [14].

In this paper, a tunable BPF is presented, which has a wide tuning range, high band pass gain, high stopband rejection, low noise figure, and low power. The paper is organized as follows. Section 2 presents the architecture and operation principle of the tunable BPF. Section 3 presents design approach to BPF for specified center frequency and bandwidth. Section 4 presents process variation aware design approach to BPF for tunable center frequency and bandwidth. BPF design calibration after process variation is also presented. Section 5 presents measurements and performance analysis of BPF after design calibration. Section 6 is the conclusion.

2. BPF Architecture and Principle Operation

The tunable BPF with differential cascade architecture is divided into two stages. Stage I is the transconductance stage. Stage II is the transimpedance stage. The transconductance stage converts input voltages and to output currents and while the transimpedance stage converts input currents and to output voltages and , as shown in Figure 1. The BPF is a type of double notch filter [2], which has two single notch filters with LC parallel series resonant combination, as depicted in Figure 2.

The input LC impedance for parallel series resonant combination is expressed as . Its small equivalent signal model is depicted in Figure 3, where the drain current of transistor (Figure 1) serves as driver of the amplifier and is the current feeding the LC parallel series resonant combination. is the current through transistor . The transconductance of is and the load resistance seen from the source of is . The input impedance is expressed in (1). Consider

Considering the parallel series LC network, its parallel resonant frequency is higher than the zero frequency , as shown below:

As shown in Figure 3, the equivalent resistance of and in parallel is approximately for . The amplitude is then expressed aswhere is equal to . Similarly, the current can be expressed by replacing with . The differential output current of the transconductance stage is simply obtained after replacing with . The same LC parallel series combination with different impedance , , is applied in the transimpedance stage with . Hence, the input impedance of the second LC stage is given byThe resonant frequencies are expressed byThe differential output voltage of the transimpedance filter stage is then expressed byWhen then . And when then . Therefore, the output current in (4) can be expressed asSimilarly, when . And when . Hence the output voltage in (6) is given by

It is observed from (9) and (10) that the transmission zero happens at in transconductance stage and happens at in transimpedance stage. Meanwhile, the peak value happens at in transconductance stage and happens at in transimpedance stage. Correspondingly, the peak conductance and impedance are obtained at and . Finally, the overall transfer function of the BPF is obtained from (3) to (9). ConsiderThe peak output can be expressed in (12) when , and also . Considerwhere and .

From (12) the peak gain happens at center frequency (the pole and the zero ). A wide tuning range is realized by changing and . A high base band gain is achieved by maximizing and , which are determined by the factor of the inductors and by location of the poles and zeros. The -factor of inductors is improved by using a cross-coupled transistor pair, creating negative impedance in parallel with the inductors. The location of poles and zeros can be adjusted by varying and .

The pole frequency can be adjusted to be slightly greater than the zero frequency by making much less than and making much smaller than . A steep roll-off can be achieved. Figure 4 demonstrates the frequency response of the proposed BPF at  GHz and BW = 12.4 MHz. Its stopband rejection is 27.4 dB. Meanwhile, the peak center frequency gain can be increased when by making .

3. BPF Design with Fixed Center Frequency and Bandwidth

Algorithm 1 presents sizing approach of BPF (Figure 1) in 180 nm CMOS process. The power supply is 1.8 V. The desirable power consumption is denoted as while the desirable center frequency and bandwidth are denoted as and BW0, respectively. With the relationship of current mirror circuit, the current drives branch currents and ; the current drives branch currents and ; the current drives branch currents and . Note that is the current through the transistor . Normally, the driver current , , is made by the tenth of its load current through transistor (, , , , , ) based on the power consumption pw.

Given: BPF (Figure 1) with NMOS ( to ), inductors (, , ), capacitors (, , , and ),
current sources (, , ), power (pw)
Input: and
Objective: BPF to meet a specified center frequency and bandwidth
Output: NMOS sizes, capacitors and inductors value
Design approach: //BPF design to meet the specified center frequency and bandwidth//
(1) Specify DC power (pw0), center frequency (), bandwidth (BW0);
(2) Calculate , and based on pw0;
(3) Set , , based on , and ;
(4)  Set initial value , and ;
(5)   Given , , , , , and ,
    set and to make a little greater than and make a little greater than ;
    set to make ;
(7)   while () //Optimize , , in iterations
(8)      ;
(9)        do DC simulation;
(10)      if /pw > 0.01 then and go to Step (7);
(11)       else exit;
(12)      end if}
(13)  adjust , , , , , ;
     do AC simulation; //find
(14)  If then go to Step (17)
(15)  else go to Step (13)
(16)  end if;
(17)  adjust ;
(18)  do AC simulation; //find BW
(19)  If /BW0 < 0.01 then exit;
(20) else go to Step (17)
(21)  end if;

The next step involves setting width and length of transistor to and multiplicand , , for current mirror load current through , , , which is precalculated and summarized in Table 1. The initial value for , , is 10. It is then optimized to have the load current through transistor (, , , , , ) as 1/10 of its driver current (, , ).

Using 180 nm CMOS process, the value of to and to is calculated based on (2), (3), (6), and (7). Given and , and are set to be a little greater than and . Also, if . The initial parameter setting is completed in steps 1–5 in Algorithm 1. As shown in Algorithm 1, , , and are optimized in step 8 till power consumption is met. Next, adjust to , , and do AC simulation until the center frequency is close to (<1% error). Finally, adjust and do AC simulation until the bandwidth BW is close to (<1% error).

4. Process Variation Aware Tunable BPF Design

4.1. Tunable BPF with Specified Center Frequency and BW

The design approach described in Section 3 is sequential and iterative loops for parameter setting and sequential results are affecting one another. The final design meets unique specifications and its design parameters are difficult to be changed to become tunable for different center frequency or bandwidth. In this regard, a design approach to make BPF tunable is proposed, which stores BPF design parameters as design reference and increases design space for wide tuning frequency range.

The design approach for tunable BPF is divided into three stages. Stage A is to meet the center frequency . Stage B is to meet the BW. Stage C is to calibrate the BPF design to meet and BW after process variations. They are shown in Figure 5. Algorithm 2 depicts detailed design approach in the three stages and explains how to obtain design parameters for the tunable BPF. In stage A, it is desirable to narrow the range of design parameters, which are primarily related to the center frequency. By referring to a look-up table of inductors (Table 2), peak pass band gain and minimum BW for different center frequencies in a wide tuning frequency range are obtained. These parameters are obtained by design approach in Algorithm 1. Given to tunable BPF design, the first step is to find the adjacent center frequency (i.e., upper and lower ) from Table 2. Next, find the upper and lower inductor from and , respectively. For example, if  GHz, then is 1.58 GHz and is 1.78 GHz. Also,  nH and  nH. Thereafter, set the initial value , . Calculate to value from equations in Section 2. Make , and do AC simulation. and are the primary impact factors to determine the center frequency. If (i.e., 15 MHz), decrease and by and then conduct AC simulation. Otherwise, decrease the second primary impact factor by until (i.e., 1 MHz). Then, go to stage B to meet the specified bandwidth, as shown in steps 11–17 in Algorithm 2. If , then BW is out of design range. Otherwise, decrease by and do AC simulation till (i.e., 0.1 MHz).

Given: , BW0, and initial values of , , .
Input: and
Objective: tunable BPF to meet and BW0
Output: , ,
Design approach: //Stage A to meet the specified (Steps (1)–(10))//
(1) Find the range of () in Table 2;
(2) Set initial values , , and set , , , , , , , , , , ;
(3)  Repeat
(4)  do AC simulation;
(5)  decrease by ;
(6)  Until ;
(7)  Repeat
(8)    do AC simulation;
(9)    decrease by ;
(10)   Until ;
Design approach: //Stage B to meet the specified BW0 (Steps (11)–(17))//
(11) Find and its corresponding BWmin in Table 2;
(12) If BW0 < BWmin then break;
(13) Else
(14) Do {
(15)   decreases inductor by ;
(16)   do AC simulation to find the bandwidth BW;
(17) } While ;
Design approach: //Stage C to calibrate BPF design after considering process variations (Steps (18)–(32))//
(18) Select (i.e., ) cases of BPF designs with different , BW0 and after Stage A and B;
(19)   Perform Monte Carlo analysis to obtain and for BW;
(20)  Compute ()); //calculate the BW deviation
(21)   Choose top 30% cases having the worst BW deviation and find their center frequency () and corresponding gain ();
(22) Compute the average of center frequency () and gain deviation ()
(23) Compute from (17);
(24) For to 30 //consider the top 30 cases
(25)  ;
(26)  do AC simulation;
(27)  if BWnew() > BWold() then set BW() = BWnew();
(28)  else ;
(29)    do AC simulation;
(30)    set BW() = BWnew()};
(31)  end if;
(32) End for;

Then, the specified BW is met. , , and are the number of repeats determined by the accuracy (, , ) in simulation. Consider

4.2. Design Example of a Tunable BPF for (1.7 GHz) and BW (12.4 MHz)

Table 3 summarizes transistor sizes and parameter settings based on the design approach in Section 3. Prior to implementing the tunable BPF design, the desirable center frequency (1.7 GHz) and BW (12.4 MHz) are specified. The number of repeats depends on the design accuracies , , and . For example, , , and are given 15 MHz, 1 MHz, and 0.1 MHz and the number of repeats , and is 20, 40, and 25. As shown in Table 2, the center frequency (1.7 GHz) lies between (1.58 GHz) and (1.78 GHz), the corresponding inductor lies between (136 nH) and (118 nH), and the inductors and lie between (0.4 nH) and (0.5 nH). Therefore, set the initial value  nH,  nH, and  pF,  pF,  pF,  pF,  pF,  pF and do AC simulation. If (>15 MHz), decrease and by  nH and then do AC simulation. Otherwise, decrease the second primary impact factor by  pF until (<1 MHz). After the specified is met, then go to stage B to meet the specified BW = 12.4 MHz.

As shown in steps 11–17 in Algorithm 2, the first step is to find and its corresponding bandwidth (). If , then BW is out of range. If , decrease by  nH and run AC simulation. Repeat until   (<0.1 MHz). Then, (1.7 GHz) and BW (12.4 MHz) are met. The proposed BPF provides a high pass band gain between 45.2 and 65.1 dB and tunable pass band between 5.5 and 51.2 MHz, while the center frequency is varied from 1.0 to 2.04 GHz, which is depicted in Figure 6.

4.3. BPF Calibration after Process Variations

The BPF design calibration to meet the specified BW after process variation is presented in stage C in Algorithm 2. The initial step in stage C is to select (i.e., ) cases of different , BW, and and conduct Monte Carlo simulation to obtain BW’s mean and standard deviation (). The top 30% design cases contributing to the worst deviation of are selected to calculate the average center frequency and the corresponding gain deviation (). Then, can be calculated from (17). Note that is used to calibrate , which in turn calibrates BW. Finally, calibrated and calibrated BW for each case are obtained. Table 4 shows the tunable BPF BW comparison with and without calibration after process variations. Ten design cases of center frequency which varied from 1 to 2.04 GHz are compared. Their BW is close to 12.3 MHz. Considering the case example of  GHz and BW = 12.2 MHz in Table 4, the bandwidth deviation before calibration is 0.88 MHz and after calibration is 0.42 MHz, which accounts for 52.3% improvement. Consider all 10 case examples, the average bandwidth deviation before calibration is 0.58 MHz and after calibration is 0.292 MHz, which accounts for 49.6% improvement.

5. Measurement and Performance Analysis

The performance of ten tunable BPF designs with the pass band nearly constant (12.1–12.6 MHz) is shown in Table 5. The bandwidth is 12.1 MHz, 12.3 MHz, 12.1 MHz, 12.1 MHz, 12.2 MHz, 12.3 MHz, 12.2 MHz, 12.4 MHz, 12.5 MHz, 12.6 MHz, and 12.6 MHz, respectively. The center frequency is varied from 1.0 to 2.04 GHz: 1.0 GHz, 1.07 GHz, 1.15 GHz, 1.20 GHz, 1.26 GHz, 1.35 GHz, 1.45 GHz, 1.58 GHz, 1.78 GHz, and 2.04 GHz. The nominal pass band gain before considering process variations is between 53.4 and 59.9 dB. Considering process variations on , , and with a maximum 10% variation on their nominal values, the Monte Carlo simulation results show robustness of the BPF: zero deviation on center frequency. The average maximum deviation on pass band gain is 1.16 dB on a nominal pass band gain of 55.6 dB. And the average maximum deviation on bandwidth is 1.06 MHz on a nominal bandwidth of 12.3 MHz.

Table 6 summarizes the calibrated performance of the ten tunable BPF designs after process variations. Figure 7 shows a low noise figure (<6 dB), while the center frequency is varied from 1.0 to 2.04 GHz.

6. Conclusion

This paper presented an effective design approach to optimize design parameters of a BPF to achieve tunable center frequency and bandwidth in a wide frequency span, for example, 1.04 GHz. Process variations on channel length, physical oxide thickness, and threshold voltage were considered in Monte Carlo simulation. The BPF design calibration to compensate bandwidth deviation from process variations was presented and evaluated. Considering process variations in 180 nm CMOS process and the central frequency which varied from 1.0 to 2.04 GHz, it was shown in Table 6 that the BW deviation is 0.292 MHz on the pass band mean of 12.01 MHz. The pass band gain variation () is 0.58 dB on the pass band gain mean of 55.02 dB. Low noise figure (<6 dB) and steep roll-off high stopband rejection (>20 dB) make the tunable BPF attractive in reconfigurable RF and cognitive radio in TV band applications.

Conflict of Interests

The authors declare that there is no conflict of interests regarding the publication of this paper.