Network-on-chip- (NoC-) based application-specific systems on chip, where information traffic is heterogeneous and delay requirements may largely vary, require individual capacity assignment for each link in the NoC. This is in contrast to the standard approach of on- and off-chip interconnection networks which employ uniform-capacity links. Therefore, the allocation of link capacities is an essential step in the automated design process of NoC-based systems. The algorithm should minimize the communication resource costs under Quality-of-Service timing constraints. This paper presents a novel analytical delay model for virtual channeled wormhole networks with nonuniform links and applies the analysis in devising an efficient capacity allocation algorithm which assigns link capacities such that packet delay requirements for each flow are satisfied.

Zvika Guz

Isask'har Walter

Evgeny Bolotin

Israel Cidon

Ran Ginosar

Avinoam Kolodny

Network Delays and Link Capacities in Application-Specific Wormhole NoCs

As CMOS technology scales down into the deep-submicron (DSM) domain, the costs of design
and verification for Systems-on-Chip (SoCs) are rapidly increasing. Relaxing the requirement of <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mn>100</mml:mn><mml:mi>&#x0025;</mml:mi></mml:mrow></mml:math> correctness
for devices and interconnects drastically reduces the costs of design but, at the same time, requires
SoCs to be designed with some degree of system-level fault-tolerance. Towards this end, this paper introduces a
novel communication paradigm for SoCs, called <em>stochastic communication</em>. This scheme separates communication
from computation by allowing the on-chip interconnect to be designed as a reusable IP and also provides a
built-in tolerance to DSM failures, without a significant performance penalty. By using this communication
scheme, a large percentage of data upsets, packet losses due to buffers overflow, and severe levels of synchronization
failures can be tolerated, while providing high levels of performance.

Paul  Bogdan

Tudor  Dumitra&#351;

Radu  Marculescu

Stochastic Communication: A New Paradigm for Fault-Tolerant Networks-on-Chip

Novel CMOS current mode shapers for front-end electronics are proposed. In particular, six semi-Gaussian shaper implementations based on second generation current conveyors and operational transconductance amplifiers are designed using advanced filter design techniques. Although all shaper architectures are fully integrated, they satisfy a relatively large peaking time. The topologies are analytically compared in terms of noise performance, power consumption, total harmonic distortion (THD), and dynamic range (DR) in order to examine which is the most preferable in readout applications. Design technique selection criteria are proposed in relation to the shaper structures performance. Analysis is supported by simulations results using SPICE in a 0.6 <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>&#x03BC;</mml:mi></mml:math>m process by Austria Mikro Systeme (AMS).

Thomas  Noulis

Constantinos  Deradonis

Stylianos  Siskos

Advanced Readout System IC Current Mode Semi-Gaussian Shapers Using CCIIs and OTAs

<i>Networks on Chips (NoCs)</i> are required to tackle the increasing delay and poor scalability issues of bus-based communication architectures. Many of today's NoC designs are based on single path routing. By utilizing multiple paths for routing, congestion in the network is reduced significantly, which translates to improved network performance or reduced network bandwidth requirements and power consumption. Multiple paths can also be utilized to achieve spatial redundancy, which helps in achieving tolerance against faults or errors in the NoC. A major problem with multipath routing is that packets can reach the destination in an out-of-order fashion, while many applications require in-order packet delivery. In this work, we present a multipath routing strategy that guarantees in-order packet delivery for NoCs. It is based on the idea of routing packets on partially nonintersecting paths and rebuilding packet order at path reconvergent nodes. We present a design methodology that uses the routing strategy to optimally spread the traffic in the NoC to minimize the network bandwidth needs and power consumption. We also integrate support for tolerance against transient and permanent failures in the NoC links in the methodology by utilizing spatial and temporal redundancy for transporting packets. Our experimental studies show large reduction in network bandwidth requirements (36.86<mml:math id="E1" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>%</mml:mi></mml:math> on average) and power consumption (30.51<mml:math id="E2" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>%</mml:mi></mml:math> on average) compared to single-path systems. The area overhead of the proposed scheme is small (a modest 5<mml:math id="E3" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>%</mml:mi></mml:math> increase in network area). Hence, it is practical to be used in the on-chip domain.

Srinivasan Murali

David Atienza

Luca Benini

Giovanni De Micheli

A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Gaurantees

Two network-on-chip (NoC) designs are examined and compared in this paper. One design applies a bidirectional ring connection scheme, while the other design applies a code-division multiple-access (CDMA) connection scheme. Both of the designs apply globally asynchronous locally synchronous (GALS) scheme in order to deal with the issue of transferring data in a multiple-clock-domain environment of an on-chip system. The two NoC designs are compared with each other by their network structures, data transfer principles, network node structures, and their asynchronous designs. Both the synchronous and the asynchronous designs of the two on-chip networks are realized using a hardware-description language (HDL) in order to make the entire designs suit the commonly used synchronous design tools and flow. The performance estimation and comparison of the two NoC designs which are based on the HDL realizations are addressed. By comparing the two NoC designs, the advantages and disadvantages of applying direct connection and CDMA connection schemes in an on-chip communication network are discussed.

Xin  Wang

Jari  Nurmi

Comparison of a Ring On-Chip Network and a Code-Division Multiple-Access On-Chip Network

A low-cost low-power DTV tuner for current digital television application is described. In order to increase integration level and reduce power consumption for off-air DTV tuner application, an SAW-filterless tuner front-end architecture is adopted. As a part of the concept, key building blocks for this architecture are implemented on a main stream 0.35 <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>&#x03BC;</mml:mi></mml:math>m CMOS technology. Experimental measurements for the prototype chip validate the system architecture; the prototype consumes 300 mw and achieves 45 dB of image rejection ratio within the entire 750 MHz frequency band.

Jianhong  Xiao

Guang  Zhang

Tianwei  Li

Jose  Silva-Martinez

Low-Power Fully Integrated CMOS DTV Tuner Front-End for ATSC Terrestrial Broadcasting

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