Active and Passive Electronic Components

Volume 2013 (2013), Article ID 813518, 11 pages

http://dx.doi.org/10.1155/2013/813518

## Influence of Series Massive Resistance on Capacitance and Conductance Characteristics in Gate-Recessed Nanoscale SOI MOSFETs

^{1}Faculty of Engineering, Jerusalem College of Technology, Jerusalem 91160, Israel^{2}Faculty of Engineering, Bar-Ilan University, Ramat Gan 52900, Israel

Received 12 June 2013; Revised 30 September 2013; Accepted 1 October 2013

Academic Editor: Gerard Ghibaudo

Copyright © 2013 Avraham Karsenty and Avraham Chelly. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

#### Abstract

Ultrathin body (UTB) and nanoscale body (NSB) SOI MOSFET devices, having a channel thickness ranging from 46 nm (UTB scale) down to 1.6 nm (NSB scale), were fabricated using a selective “gate recessed” process on the same silicon wafer. The gate-to-channel capacitance and conductance complementary characteristics, measured for NSB devices, were found to be radically different from those measured for UTBS. Consistent and trends are observed by varying the frequency , the channel length , and the channel thickness (). In this paper, we show that these trends can be analytically modeled by a massive series resistance depending on the gate voltage and on the channel thickness. The effects of leakage conductance and interface trap density are also modeled. This modeling approach may be useful to analyze and/or simulate electrical behavior of nanodevices in which series resistance is of a great concern.

#### 1. Introduction

Planar Fully-Depleted Silicon-On-Insulator (FD-SOI) technology relies on a silicon wafer having an ultrathin layer of crystalline silicon smartly built over a Buried Oxide layer (commonly called BOX). Transistors built into this top silicon layer (which thickness ranges in the decananometer thickness) are called Ultrathin Body (UTB) devices. Such devices have unique and extremely attractive characteristics for coming technology nodes. Since performance needs are increased together with power consumption control, UTB/FD-SOI is also a key technology for addressing high speed and leakage control. In the past several years this technology has gained significant momentum in the mobile communications market space [1, 2]. FD-SOI devices were deeply analyzed across the literature, including the influence of the BOX/Si interface [3]. However, if characterization and modeling of gate-to-channel capacitance and conductance in FD-SOI devices were recently presented [4], the analyses were focused on devices with gate lengths down to 35 nm and channel thickness down to 8 nm. In parallel, characterization and parameter extraction methods [5, 6], including CV-based method [7], were developed to emphasize dependences between parameters.

In this paper, we report the influence of the silicon channel thickness on the - characteristics of Nanoscale Body (NSB) SOI MOSFET devices having a channel thickness less than 5 nm and obtained by a selective gate recessed process [8]. We present a semiquantitative model allowing to justify the influence of the series resistance and to discriminate the influence of the surface states on the - characteristics. A preliminary unified electrical model was recently presented in a previous work [9] in which UTB's - characteristics in the linear region were compared to those of NSB. The cross-sections of these device structures are, respectively, shown in Figures 1 and 2. The NSB’s - characteristics were interpreted as the result of an extreme parasitic drain-source series resistance. Since this parameter is of major concern for modern nanoscale devices, its quantitative influence on electrical properties is important to modeling. Usually, drain-source series resistance is aimed to be minimized but design, process, or/and material related issues can generate such parasitic phenomenon that influences the electric properties [10]. In addition to last years' existing knowledge in series resistance, these novel interpretative approach and analytical model can be useful for the prediction of transport phenomena at the nanoscale.

#### 2. Device Processing

##### 2.1. SIMOX Preferred Wafer Processing Technology

Today, SOI wafers are mainly fabricated using the UNIBOND line of SOI wafers and the Smart Cut process technologies, patented by SOITEC Company, allowing excellent thickness uniformity [11]. However, for this research purpose, the former SOITEC technology called Separation-by-IMplanted-Oxygen (SIMOX) was chosen because of the clear advantage of presenting an initial gradient of the SOI thickness across the same wafer. This desirable gradient is conserved during the processing of the nanoscale Body devices (NSB) as shown in Figure 3, in which postthinning spectrophotometry measurements of SOI thicknesses gradient, using the gate recessed process, are presented across a diameter SIMOX test wafer. Consequently, it is now possible to study the thickness influence on the NSB electrical characteristics with a single process run. The accuracy of the critical channel thickness of 1.6 nm was confirmed by in ex situ HRTEM measurement (Figure 2).

##### 2.2. Structural Characterization

Both representative SOI MOSFET devices having a same ratio W/L of 80/8 (*µ*m) were analyzed using FIB and HRTEM techniques. A FIB cross-section of the Ultrathin Body Device (UTB) (46 nm channel thick) is presented in Figure 1 showing the device structure (Figure 1(a)) and the morphology of the layers forming the gate region (Figure 1(b)). A HRTEM zoom-in of the recessed silicon channel for the nanoscale Body Device (NSB) is presented in Figure 2, confirming the 1.6 nm thickness value.

##### 2.3. Thickness Characterization

The most challenging step was the accurate controlled thinning process of the SOI layer using local oxidation in the sub 10 nm range of thickness, while the source and the drain regions remained in their original thickness. In order to check the capability of accurate thinning, preliminary tests were performed in order to reach thicknesses lower than 10 nm, when characterizing the furnace parameters such as furnace temperature, duration of the oxidation, and growth rate [12].

##### 2.4. Gate Recessed Process

The local oxidation was performed by using a nitride mask layer of 38 nm (nitride 1) grown on a thin oxide layer (PAD OX) of 15 nm. The role of the pad oxide was to serve as an interface between the nitride and the silicon to prevent mechanical stresses. A first etching of the nitride and pad oxide layer at the extremities of the active region allowed their oxidation into a 700 nm thick Field Oxide (FOX). A second etching, performed at the center of the nitride region, allowed exposure of the channel region while the surrounding nitride capped the source and drain areas. Two steps of oxidation were then performed: First, a 75 nm thick sacrificial oxide layer, called Channel Oxide (CHAN OX), was grown in order to significantly decrease the channel’s thickness to about 10 nm, before removal. The second phase of the oxidation (25 nm thick), called Gate Oxidation (GOX), was a more accurate step, making possible a final nanoscale thickness of the channel, in the range of 1.6 nm to 6.5 nm, and serving as the Gate Oxide itself. The thickness distribution uniformity and the Si-SiO_{2} interface quality [14] serve as important parameters [15, 16]. In order to get reference devices, that is, having an initial silicon channel close to 46 nm, the nitride mask was not etched so the gate insulator layer is made of the 38 nm thick nitride layer deposited on the 15 nm PAD OX layer.

##### 2.5. Drain-Source Contacts Fabrication

A polycrystalline silicon layer of 220 nm was deposited over the gate oxide, oxidized, and patterned to form the gate electrode. Before the source/drain/gate phosphorus implant, a thin layer nitride (nitride 2) of 30 nm was deposited in order to prevent further oxidation of the thin silicon layer during the implant's thermal annealing. A Plasma Enhanced Chemical Vapor Deposition (PECVD) oxide (silox 2) of 350 nm thickness was deposited followed by an aluminum metallization step to define the contact areas.

#### 3. Electrical Characterizations and Analysis

##### 3.1. Measured Resistance as a Function of Channel Length

The measured resistance is defined as the slope of the - characteristics taken in the linear domain for a given gate voltage . In Figure 4, is plotted as a function of different gate lengths ( *µ*m, 6 *µ*m, 8 *µ*m, and 100 *µ*m) for two NSB’s devices (1.6 nm and 2.4 nm channel thick) and for two gate voltages (0 V and 4 V) both above the threshold voltage. For these devices, is decreased by increasing . Surprisingly, is found almost constant with . In contrast, the UTB reference devices (46 nm channel thick, for *µ*m, 8 *µ*m, and 100 *µ*m) exhibit a linear - trend and a decreasing trend with as expected from the classic MOSFET’s channel resistance [17, 18]. This result indicates that the contribution of the channel resistance may be negligible for the NSB devices. Assuming is a serial association of with the series source-drain resistance, then can be then approximated by . For NSB’s devices, is ranging between 100 kΩ and 1 MΩ and is decreasing with the channel thickness as already modeled in a previous work [9].

Although series resistance is usually considered as an association of contributions such as sheet contact resistance, spreading resistance, and other “wire resistance” [19, page 223–225], none of these contributions exhibits the experimental trends observed for NSB’s devices here. In our case, the measures resistance should be related to another scattering phenomenon that we propose to investigate using - measurements.

##### 3.2. Gate to Channel Capacitance and Conductance Characteristics as a Function of Channel Thickness for ** ***µ*m

The gate to channel capacitance (CGC) of the devices was measured as a function of the Gate voltage using a dual frequency (100 kHz or 1 MHz) CV analyzer (Keithley Model 590). Source and Drain contacts are connected together while the backside (substrate) contact is kept grounded. The DC bias is applied to the drain-source contact and ac-current is collected through the gate contact. The experimental setup is the same as in [13] and shown in Figure 5.

The measured NSB devices, sharing the same (80/100 *µ*m) but different channel thicknesses (1.6 nm and 3.3 nm), are compared to UTB reference device (46 nm channel thick). For all the devices, the measurement was performed at 100 kHz and 1 MHz using the parallel extraction model. The corresponding gate-to-channel capacitance and conductance versus are presented for 100 kHz in Figures 6(a) and 6(b), respectively. The corresponding gate-to-channel capacitance and conductance are presented for 1 MHz in Figures 6(c) and 6(d), respectively.

For the reference UTB device (E15: 46 nm), as seen in Figure 6(a), the negative domain corresponds to the *accumulation zone* (cut-off regime) where parasitic and gate overlap capacitances are measured to be about 4 pF. Between −1 V and 0 V, the raising of the capacitance is due to the *depletion zone* below the threshold voltage . In the positive domain, the - characteristic of the UTB’s reference device (E15: 46 nm) saturates, which is corresponding to the *inversion zone* [20–22]. The capacitance step amplitude (8 pF), almost independent of the measurement frequency (as seen in Figure 6(c)), is found about 20% lower than the expected total gate oxide capacitance value (9.7 pF) for a area of cm^{2} ( (UTB) = 121 nF/cm^{2}). This discrepancy may be related to a calibration or a dispersion issue. Another reason we could argue is the additive relative experimental errors we have on the dimensional parameters of the capacitance like , and/or layer thicknesses. Then, by assuming a reasonable 5% error value for each parameter, it may be realistic that our capacitance is estimated with such 20% error. In Figure 6(b), the conductance exhibits a double peak in the depletion zone which is characteristic of the presence of interface states distributed throughout the silicon channel band gap [19, page 337]. By increasing the frequency to 1 MHz, this double peak is enhanced near zero voltage as seen in Figure 6(d).

For the NSB's devices (E15: 1.6 nm and D04: 3.3 nm), as seen in Figure 6(a), the - characteristic is shifted relatively to the UTB’s one, but the capacitance step amplitude is found a bit lower than the former one (6-7 pF). For the D04 device, a hump is observed in the depletion region near zero voltage. This is closely related to the hump of the corresponding - characteristic shown in Figure 6(b) which is in turn related to the presence of additional interface states as mentioned above. In Figure 6(b), for NSB devices, the conductance amplitude step is about four times those measured for the UTB’s one. The NSB's conductance decays through the positive voltage range but with a slower rate than for UTB’s.

When increasing the frequency from 100 kHz to 1 MHz, as seen in Figures 6(c) and 6(d), for NSB’s, the capacitance step amplitude (~10 pF) and (~1 *µ*S) is increased and decreased by one order of magnitude respectively. Moreover, at 1 MHz, in contrast to 100 kHz, both the capacitance and the conductance are increasing with positive voltage.

##### 3.3. Gate to Channel Capacitance and Conductance Characteristics as a Function of Channel Thickness for ** ***µ*m

The measured NSB devices, sharing the same (80 *µ*m/8 *µ*m) but different thicknesses (1.6 nm and 3.3 nm), are compared to UTB (46 nm thick). The corresponding gate-to-channel capacitance and conductance as a function of are presented for 100 kHz in Figures 7(a) and 7(b), respectively. The corresponding gate-to-channel capacitance and conductance are presented for 1 MHz in Figures 7(c) and 7(d), respectively.

For the UTB reference device (E15: 46 nm), as seen in Figures 7(a) and 7(c), the capacitance step amplitude (0.4 pF) is almost independent of the measurement frequency. This amplitude is about half the expected total gate oxide capacitance value (0.77 pF), which corresponds to a area of cm^{2} ( (UTB) = 121 nF/cm^{2}). This discrepancy may be related to a lack of accuracy as mentioned above and in particular for the sub-pF range. In contrast to Figure 6(a), at 100 kHz and for positive voltage, the NSB’s capacitance characteristics appear strongly degraded comparatively to the UTB’s ones and exhibit a maximum value near zero voltage. This degradation is enhanced at higher frequency (1 MHz) and for the lowest channel thicknesses. As seen in Figure 7(b) and unlike Figure 6(b), the conductance for UTB’s is found constant with and insensitive to the frequency change (Figure 7(d)). This indicates a low density of interface states. However, at 1 MHz, a peak of conductance is observed for NSB’s around zero voltage. By examining the order of magnitudes of the capacitance step amplitude (~1 pF) and conductance baseline (~1 *µ*S), we noticed that, by increasing the frequency from 100 kHz to 1 MHz, is decreased by a factor of two while is strongly increased by one order of magnitude. Comparatively to Figure 6 (for *µ*m), the effect of the frequency on and is found weaker.

#### 4. Modeling and Interpretation of the Results

##### 4.1. Modeling the Gate-to-Channel Capacitance and Conductance Characteristics

In order to give a physical interpretation of the measured trends in Figures 6 and 7 and take into account the effect of a series resistance, we propose here to use a classical model of the relationships between the gate-to-channel capacitance and conductance measured in parallel mode. In a first analysis, we will omit the influence of interface states which will be considered in the next section. Since a series resistance effect is expected to influence our measurements, as shown above from Figure 8, we have to consider the following electrical equivalent circuits.

In Figure 8(a), the actual gate to channel capacitance is coupled with a parallel conductance , related to a leakage phenomenon, and associated with series resistance .

Assuming a parallel equivalent circuit of two elements (Figure 8(b)), the measured capacitance and conductance are given by the following equations [19, page 89]: where kHz or 1 MHz).

In case of a low leakage conductance and/or low series resistance we get

Note that, in this case, for a low factor (low frequency and/or low value) and tend, respectively, to their actual values and .

In case of a low leakage conductance and/or high series resistance , (1) can be approximated by

Note that, in this case, for a low factor (low frequency and/or low value) and tend, respectively, to and .

According to the above equations, we can expect the separate influence of each of the three factors on the measured and values for a given . Assuming a high and low values set for each factor, we can design a two-level factorial design plan [23] including eight combinations (trials) of the three factors (see Table 1). The expected orders of magnitude (actual value) are pF (for *µ*m) and pF (for *µ*m). These values are estimated from the respective oxide gate capacitance of the devices as measured in the inversion zone. The orders of magnitude of the factor series resistance are 100 Ω (low value for UTB device) and 100 kΩ (high value for NSB device) as expected from Figure 4. Considering that we have low leakage devices, as checked from - characteristics (not shown here), the low and high values of are chosen to 0.5 *µ*S and 5 *µ*S, respectively. These values are matched with those measured for the shorter devices at low frequency and high frequencies in Figures 7(b) and 7(d), respectively. Then, the modeled values of and are presented in Table 1.

In a factorial design plan it is usual to define the *factor effect* (frequency, series resistance, and leak conductance) on the modeled or values as follows:
where
In order to highlight the expected trends according to (1), the respective factor effects are calculated and normalized to the average value of and , respectively, and given in percent units as presented in Table 1.

The semiquantitative effects of the frequency and the series resistance on and in the inversion zone (positive gate voltage), as observed from Figures 6 and 7, are indicated for comparison in the last rows of Table 1.

In Figures 6(a) and 6(b) ( *µ*m, kHz), the measured capacitance was weakly decreased while was increased by a factor of four between UTB and NSB devices.

Moreover, we noticed that while increasing the frequency from 100 kHz to 1 MHz the measured capacitance for NSB's was strongly decreased by one order of magnitude while is increased also by one order of magnitude. From Table 1 we can see that this trend is simulated for the modeled values when the factor is at its high value and almost independently of the (leak) values (rows 3 and 4 and rows 7 and 8). This confirms the detrimental influence of series resistance on the - characteristics in particular for thinner channels (NSB) for which the values are increased. Moreover, the increasing of the NSB’s conductance with gate voltage at high frequency (Figure 6(b)) can be related to the decreasing of the with gate voltage as seen in Figure 4. From (4), we can see the analytical link between and the factor.

For shorter devices having *µ*m (and then lower ) Table 1 confirms the weaker influence of series resistance on the - characteristics independently of the (leak), in particular for the thinnest channels (1.6 nm) for which the is enhanced. Indeed, the influence of the frequency on modeled is lower (see small change between rows 3 and 4 and between rows 3 and 4) than for *µ*m.

##### 4.2. Influence of the Interface Trap Capacitance on the Gate to Channel Capacitance and Conductance Characteristics

In order to interpret the peak of conductance observed in the depletion zone in Figures 6 and 7, we need to modify the actual circuit to take into account the effect of the interface states [19, page 373–375] as shown in Figure 9. Here we assume the effect of interface trap to a pure capacitance effect though it is usual to associate another parallel resistance in order to take into account the time response of the trapping process. However, this approximation is valid for high enough frequencies (above 10 kHz).

Assuming a parallel equivalent circuit of two elements (Figure 9(b)), the measured capacitance and conductance given by (1) can be modified to get the following equations: where and is the interface trap densities.

Considering that we have low leakage devices and since is not an influent factor in this range, is fixed to 0.5 *µ*S. Then, according to the above equations, we can check the separate influence of each of the three factors on the measured and values for a given . Assuming a high and low values set for each factor, we can design a two-level factorial chart including eight combinations (trials) of the three factors like that in Table 1. The low and high levels of are 10^{10} cm^{−2}eV^{−1} and 10^{12} cm^{−2}eV^{−1} which are the standard range of detection of interface traps in silicon using the conductance method [19, page 373]. The corresponding parallel capacitance values are calculated according to (6) and shown in Table 2. Then, the modeled values of and are presented in Table 3.

We can notice from Table 3 that for UTB ( *µ*m) the introduction of a large value should imply an increasing of the capacitance by a factor of two, and an increasing of the conductance by a factor of ten for all measured curves at 100 kHz. By increasing the frequency to 1 MHz, the capacitance should not be increased anymore, but the conductance should be increased by a factor of five. These trends are observed in Figure 6 near zero gate voltage (depletion zone) as a hump in the capacitance step and as an additional conductance peak, respectively.

For NSB ( *µ*m), the introduction a large value should imply is a very small increase of the capacitance and of the conductance measured at 100 kHz. By increasing the frequency to 1 MHz, the capacitance should be strongly decreased by a factor of 65 but the conductance should be increased only by a factor of 1.5. These trends are observed in Figure 6 near zero gate voltage (depletion zone) as a degradation of the capacitance step and as an increasing of conductance peak, respectively.

According to Table 3, for UTB ( *µ*m) the introduction of a large value should imply an increasing of the capacitance by a factor of two, but the conductance should keep constant. An increasing of the frequency (100 kHz to 1 MHz) should not increase anymore the capacitance or the conductance. These trends are not observed in Figure 7 near zero gate voltage. Indeed the flat conductance characteristics of UTD’s show the absence of interface traps for these devices.

For NSB ( *µ*m), the introduction of a large value should imply a very small increasing of the capacitance and of the conductance, all measured at 100 kHz. By increasing the frequency to 1 MHz, the capacitance should be strongly decreased by a factor of two; however, the conductance should be increased only by a factor of ten. These trends are observed in Figure 7, near zero gate voltage. However, these effects compete with those from the series resistance as seen in Table 2. In these devices, the influence of the interface traps cannot be clearly resolved from the series resistance effect.

#### 5. Conclusions

Nanoscale (NSB) and Ultrathin (UTB) SOI MOSFET devices were fabricated using a selective gate-recessed thinning process in order to obtain channel thicknesses varying from 1.6 nm to 46 nm. Their respective gate-to-channel capacitance and conductance characteristics were found to be different and presented different trends as a function of the frequency , the channel length , and the channel thickness . In particular the frequency increasing has a positive effect on but a negative on for NSB devices but almost no effect for UTB’s. We show that these influences can be analytically and consistently modeled by the presence of a massive series resistance (in the 100 kΩ range) depending on the channel thickness and on the gate voltage. Moreover, in the depletion region of long devices ( *µ*m), near zero gate voltage, the additional peak of and observed in UTB and NSB can be attributed and modeled by an additional capacitance related to the presence of a large interface trap density at low frequency. This effect was not observed for NSB at high frequency nor for shorter devices ( *µ*m). This can be interpreted by the influence of the massive series resistance which screens the effect of the interface traps at high frequency. Finally, the interest of this study for the FD-SOI community is to provide a semiquantitative model that may be useful to interpret the non-classical electrical characteristics of such nanoscale devices.

#### Conflict of Interests

The authors have no conflict of interest is associated with this paper.

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