Research Article  Open Access
Improving Linearity and Robustness of RF LDMOS by Mitigating QuasiSaturation Effect
Abstract
This paper discusses linearity and robustness together for the first time, disclosing a way to improve them. It reveals that the nonlinear transconductance with device working at quasisaturation region is significant factor of device linearity. The peak electric field is the root cause of electron velocity saturation. The high electric field at the drift region near the drain will cause more electronhole pairs generated to trigger the parasitic NPN transistor turnon, which may cause failure of device. Devices with different drift region doping are simulated with TCAD and measured. With LDD4 doping, the peak electric field in the drift region is reduced; the linear region of the transconductance is broadened. The adjacent channel power ratio is decreased by 2 dBc; 12% more power can be discharged before the NPN transistor turnon, indicating a better linearity and robustness.
1. Introduction
Linearity and robustness are very important in power amplifier of base station communication. For LDMOS power devices, the relationship between output and input signal is close to the square relationship in saturation region, which is very prone to spectrum leakage and intermodulation distortion. In addition, the capacitance exhibits a nonlinear relationship with the voltage, which easily generates phase distortion. In communication applications, devices always work with backoff to meet linearity requirements, which sacrifice efficiency, especially for asymmetric Doherty amplifiers [1]. The adjacent channel power ratio (ACPR) is an indicator to measure the linearity of power amplifier; it is defined as the ratio of power density of the offset channel to the power density of the main channel.
The research of linearity of RF LDMOS focuses on the linearity of capacitance and transconductance. Paper [2] studied the effects of input capacitance on intermodulation distortion (IMD) and AMPM distortion under the twotone signal input of class A power amplifier from the simulation point of view. Paper [3] revealed that the lowfrequency IMD related to the nonlinearity of transconductance, while the highfrequency IMD related to the nonlinearity of transconductance and capacitor. In paper [4], multiple LDMOS were combined in parallel; each was biased at different voltages; then IMD was reduced by combination of different sweet spots. Paper [5] reduced the size of the drain contact to increase the saturation current.
Robustness is the ability of LDMOS to withstand the power from output mismatched or the power from electronstatic discharge. Robustness of LDMOS correlated with the inherently presented parasitic bipolar NPN transistor [6], and more body doping was suggested to suppress the turnon of NPN transistor. The device could fail because of formation of early filament [7, 8]; deep implantation drain contact [9] and ESD implantation at drain side [10] were suggested to address the formation of early filament issue.
This paper discusses the linearity and robustness together for the first time. Electric field distribution and transconductance of devices with different drift region doping are simulated with TCAD. The peak electric field of drift region can be reduced by adjusting the doping of drift region, resulting in better linearity and robustness, verified by silicon data. Section 2 of this thesis analyzes the relationship between transconductance and linearity, analyzes the relationship between quasisaturation effect and electric field distribution in the drift region, and proposes a scheme to improve the linearity of transconductance and robustness. The test results and discussion are shown in Section 3. And Section 4 concludes this paper.
2. Methods and TCAD Simulation
Figure 1 is a schematic diagram of the structure of LDMOS device; Figure 2 is the smallsignal equivalent circuit of the device, where is the equivalent resistance of the drift region, and is the transconductance of the device. According to the Miller effect, the transconductance of the device is represented by as shown in formula (1). The linearity can be improved in two ways, one is to improve the linearity of the transconductance, and the other is to reduce the Miller capacitance and the output capacitance . This paper optimizes the linearity of transconductance by mitigating the quasisaturation effect.
The space charge modulation effect is the cause of current saturation [11, 12]; on one hand, it decreases the mobility of electrons, and on the other hand, it narrows the depletion layer between the channel edge and the drift region. The reduction of mobility is due to the increase of electron density injected into the drift region and the peak electric field near the drain. The higher the peak electric field, the easier the carrier mobility saturated and thus the earlier the current saturation. Correspondingly, there are two methods to mitigate the saturation effect. One is to increase the background concentration, but the breakdown voltage and the reliability of the hot carrier injection will be sacrificed. The second is to reduce the drift region length, which will sacrifice the breakdown voltage and robustness. To get a good tradeoff between linearity, efficiency, breakdown voltage, HCI reliability, and robustness, the peak electric field in the drift region has to be flatten. The electric field and transconductance of different drift region structure are simulated with TCAD.
Figure 3 is a diagram of the doping structure of the drift region. The length of the drift region is 2.8 um. LDD1 indicates the first Ntype implantation in the entire drift region; the energy is 100KEV. LDD2 is the second Ntype implantation with the energy of 200KEV; the distance to the gate edge is 0.8um. LDD3 is the third Ntype implantation with the energy of 200KEV; the distance to the gate edge is 1.4um. LDD4 is the fourth Ntype implantation with the energy of 200KEV; the distance to the gate edge is 2.2μm. The dosage of each implantation is shown as L1D, L2D, L3D, and L4D in Table 1. This step doping profile structure can increase the FOM value of breakdown voltage and onresistance, especially in super junction structures [13].

Table 1 lists the doping condition and DC simulation results of device with different drift region doping. Drain saturation current increase as the total doping of drift region. As illustrated in Figure 4, transconductance and saturated drain voltage increase as doping of drift region, the saturation point shifted to a larger drain current, and the linear region of transconductance is broadened, indicating better linearity. Transconductance of device with LDD4 doping increases significantly, while only little change was found when doped with LDD3 after LDD4. It is because the electric field of the drift region is optimized with LDD4 doping; more doping would not cause significant change of the electric field and thus the transconductance. As illustrated in Figure 5, similar transconductance can be obtained, by increasing the width of LDD4 or by increasing the dose of LDD4.
The electric field distribution under quasisaturation condition is illustrated in Figure 6. The black ellipse box in the figure is the interface of drift region and the drain contact, where the peak electric field located. This peak electric field decreases after LDD4 is implanted and decreases as the number of LDD increases. The graded doping near the drain results in a uniform distribution of the electric field. The peak electric field in the drift region of device with LDD4 doping reduces significantly, resulting in a broadened linear region of transconductance. Increasing the number of LDD’s implantation reduces the peak electric field near the drain, making the electric field distribution in the drift region more uniform, reducing the saturation of the carriers, thereby mitigating the quasisaturation effect of the device.
(a) LDD1 and LDD2
(b) LDD1, LDD2, and LDD4
(c) LDD1, LDD2, LDD3, and LDD4
(d) Electric field at Y=0.01um
The electrical equivalent circuit corresponding to the robustness is given in Figure 7. Under output mismatch condition, high power returned to the LDMOS drain, leading to high drain voltage, resulting in strong electric field at the drift region. Then more electronhole pairs are generated and the hole current may trigger the conduction of NPN transistor, leading to formation of early filament [7, 8], which may cause failure of device. To improve robustness, the electric field at drift region near the drain has to be decreased to restrain the formation of electronhole pairs. As the analysis in last paragraph, the electric field at the drain can be uniformed with LDD4 doping.
It can be summarized that the doping distribution near the drain became graded distribution after LDD4 doping, which reduced the peak electric field near the drain, and uniformed the electric field in the drift region. Then the kirk effect is relaxed, thus mitigating the quasisaturation effect, resulting in a more linear transconductance. Device with more uniform distribution electric field near the drain will have fewer electronhole pairs generated under mismatch and better robustness. The linearity and robustness optimization result will be discussed in next section.
3. Results and Discussion
Referring to the HCI evaluation method of [14], device was stressed at the static biased condition; in this paper, equals 28V and equals 8mA/mm. Then onresistance and drain current were drawn versus time to evaluate the device lifetime. The onresistance and static drain current degradation of device of condition G with the maximum saturation current, which may have worse HCI, as well as condition C are given in Figure 8. The growth of onresistance within lifetime is limited to 10%, which will result in 0.3dB reduction of output power. The onresistance of condition G increases less than 6% within 20 years, which meets the lifetime requirement of base station application.
The transconductance of test structure on wafer of different devices is given in Figure 9. The transconductance increases as doping of drift region, and the saturation effect is mitigated with LDD4 and LDD3 doping, matching with TCAD simulation. As illustrated in Figure 10, 2dBc better ACPR is obtained with LDD4 doping, but no significant change of ACPR was found in device with LDD3 doping after LDD4. It can also be found in Figure 11 that, to some extent, there is no significant change of ACPR when increasing the doping of LDD3. It can be concluded that the linear region of transconductance is broadened with LDD4 doping, and 2dBc better ACPR is obtained, with very little benefit when additional LDD3 is added after LDD4.
To verify the robustness of the devices with doping engineering, devices of conditions A, C, and G are tested under transmission line pulse (TLP) test, as illustrated in Figure 12 and Table 2. With LDD4 doping, , the drain voltage when the parasitic NPN transistor turns on increases from 78 volts to 87.5 volts, which means 12% more power can be discharged, indicating better robustness. No significant change of robustness was found in device with LDD3 doping after LDD4 doping.

The transconductance measurement matches with TCAD simulation; the ACPR and robustness measurement data match with the TCAD simulation conclusion of electric field distribution. With LDD4 implantation, the concentration gradient between the drain contact and the drift region is reduced, and the gradient decreases as the dosage increases. The peak electric field of the drift region near the drain reduced, resulting in more uniform electric field distribution, which mitigated the saturation effect of the device, making a more linear transconductance, thereby improving the ACPR. Better robustness is also obtained with more uniform distributed electric field.
4. Conclusion
It is revealed and verified by TCAD simulation and measurement data that, by drift region doping engineering, the peak electric field distribution in the drift region is reduced, the quasisaturation effect of the device is mitigated, the linearity of the transconductance is improved, and the ACPR is improved more than 2 dBc. The reduction of the drain peak electric field is also beneficial to the robustness of the device; 12% more power can be discharged before the parasitic NPN transistor turns on.
Data Availability
Experimental results provided in the article were obtained in the System Integration and IC Design Division of Suzhou Institute of NanoTech and NanoBionics, Chinese Academy of Sciences, in 2018.
Conflicts of Interest
The authors declare that there are no conflicts of interest regarding the publication of this paper.
Acknowledgments
This work is supported by the National Key Research and Development Program of China (Grant No. 2016YFE0129400), the Youth Innovation Promotion Association CAS (Grant No. 2016290), the National Defense Basic Scientific Research Program of China (Grant No. JCKY2017210B006), and the Strategic Priority Research Program of the Chinese Academy of Sciences (Grant No. XDC02010800).
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Copyright
Copyright © 2019 Haifeng Mo et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.