Concepts of Novel Nanomaterial Device and ApplicationView this Special Issue
Research Article | Open Access
Investigation of Low-Frequency Noise Characterization of 28-nm High-k pMOSFET with Embedded SiGe Source/Drain
We have studied the low-frequency noise characterizations in 28-nm high-k (HK) pMOSFET with embedded SiGe source/drain (S/D) through noise and random telegraph noise measurements simultaneously. It is found that uniaxial compressive strain really existed in HK pMOSFET with embedded SiGe S/D. The compressive strain induced the decrease in the tunneling attenuation length reflecting in the oxide trap depth from Si/SiO2 interface to the HK layer, so that the oxide traps at a distance from insulator/semiconductor interface cannot capture carrier in the channel. Consequently, lower noise level in HK pMOSFET with embedded SiGe S/D is observed, thanks to the less carrier fluctuations from trapping/detrapping behaviors. This result represents an intrinsic benefit of HK pMOSFET using embedded SiGe S/D in low-frequency noise characteristics.
Low-frequency noise is an important issue for analog, digital, mixed signal, and RF application. Nowadays, complementary metal-oxide-semiconductor (CMOS) technology has intruded into RF and/or analog circuits, and hence the excessive low-frequency noise will lead to a limitation of the functionality for related circuits [1, 2]. Low-frequency noise, including flicker (1/) noise and random telegraph noise (RTN), is increasingly attracting much interest in the CMOS device and technology community. In metal-oxide-semiconductor field-effect transistor (MOSFET) devices, the origin of 1/ noise and RTN is considered stemming from the carrier behaviors related to the oxide traps. 1/ noise is most often due to fluctuations in carrier number and/or carrier scattering [3, 4]. RTN is another special kind of noise, which also appears in a low-frequency spectrum and originates from the trapping/detrapping behavior of a single or few traps [5, 6].
On the other hand, the continued shrinking of conventional CMOS to enhance device performance has revealed limitations. The mobility enhancement has emerged as a key technology for improving drive current . Ways of optimizing channel mobility had been proposed to overcome the limitations on the scaling down of devices and to further improve the speed of CMOS circuits. The introduction of channel strain engineering in the state-of-the-art CMOS technology is recognized as an indispensable performance booster in producing next generation CMOS devices [8, 9]. For p-type MOSFET (pMOSFET), using embedded SiGe in the recessed source/drain (S/D) region can efficiently provide uniaxial compressive strain in the channel and improve hole mobility, bringing the enhancement of device performance [10–12]. In addition, high-k (HK) materials are also adopted into advanced CMOS process for solving the increased gate leakage current. This is because HK dielectrics are the promising candidate for gate insulator to achieve low equivalent oxide thickness as required for the advanced CMOS technology nodes . However, a fabricated pMOSFET with SiGe S/D is possibly accompanied by the extra amount of process-induced defects, and a gate insulator that is replaced from conventional SiO2 to HK materials usually causes the changes of trap properties in MOSFET, resulting in the influence on low-frequency noise characterizations. Though low-frequency noise characterizations in pMOSFET with SiGe S/D had been reported [12, 14], low-frequency noise in HK pMOSFET with SiGe S/D is still unclear and needs to be addressed to improve the understanding. In this study, the low-frequency noise characterizations of HK pMOSFET with embedded SiGe S/D are investigated through 1/ noise and RTN measurements simultaneously.
Apart from the S/D engineering, a 28-nm HK first/meta gate last technology was used to prepare the pMOSFET samples for this work. The thickness of the SiO2 interfacial layer was approximately 1.0~1.1 nm. A total of 20 atomic layer deposition cycles for HfO2 were deposited on the top of the SiO2 interfacial layer, and the thickness of all gate stacks was approximately 1.6~1.7 nm. A thin TiN layer was deposited on HfO2 layer as a capping layer for selective removal of the dummy poly-Si gate . After the S/D activation is annealed, the dummy poly-Si gate was removed and then other metals were deposited to tune the work function and achieve the idea value (5.0~5.2) . The strained-Si HK pMOSFET structure features improvement by optimizing S/D recess shape following an epitaxially grown B-doped SiGe film embedded in the S/D regions with about 30% Ge concentration. Finally, the devices were completed with standard backend processes. The HK device without embedded SiGe was also fabricated and called as control device for comparison. The values of oxide capacitance derived from the equivalent oxide thickness of the CVC program  are 2.801 × 10−6 and 2.746 × 10−6 F/cm2 for the control and the SiGe S/D devices, respectively. All the pMOSFETs with the gate dimension of were used in this work. Prior to low-frequency noise measurements, the dc characteristics were measured using an Agilent B1500 semiconductor parameter analyzer. The 1noise measurements were carried out using SR570 low-noise current preamplifiers and an Agilent 35670A dynamic signal analyzer. The pMOSFETs were biased in linear operation while varying the gate overdrive voltage from the subthreshold regime (0.2 V) to the inversion regime (−0.3 V). The RTN measurements were made by waveform generator/fast measurement unit modules based on Agilent B1500 semiconductor parameter analyzer.
3. Results and Discussion
Figure 1 shows the drain current () as a function of the drain voltage () for both pMOSFETs. Around 18% enhancement for SiGe S/D device is observed as compared to the control device at the same, and , which clearly indicates that the embedded SiGe S/D process can efficiently induce compressive strain in the channel. Figure 2 presents the drain current noise spectral density () versus the frequency for both pMOSFETs taken from the average of six devices biased at different . Both devices show typical 1/ noise types with the frequency exponent () close to unity. It means that the fluctuations of 1/ noise can be attributed to the carrier-number, mobility, or source-drain series-resistance fluctuations. In our devices, the was found to be independent of the , indicating that the 1/ noise source is not due to the contact or source-drain series resistance. The normalized drain current noise spectral density and the transconductance to the drain current squared () as functions of the are plotted in Figure 3. The curves of both devices show fairly good proportionality with at the low level, indicating that the carrier number fluctuation dominates the 1/noise, which caused by trapping and releasing of the carrier in the gate stacks [4, 5]. However, the curves cannot follow this trend at the high level, which implies a correlated mobility fluctuation was involved [6, 18]. In order to further evaluate the dominant mechanism and parameters of the 1/ noise model for both devices, the normalized input-referred voltage noise spectral density as a function of is shown in Figure 4. Both devices show two distinct regions in the associated . In region I , is independent of , which indicates a signature of umber fluctuations. In region II , a parabolic dependence of on () is observed, further confirming that correlated mobility fluctuations was involved. These results mean that the main source of 1/ noise for both devices can be ascribed to the unified model, which incorporates both the carrier number and the correlated mobility fluctuations. Furthermore, the can be expressed as  where is the tunneling attenuation length for channel carriers penetrating into the gate dielectric, is the oxide trap density, is a scattering coefficient, and is the low field mobility. The first term in the parentheses in (1) determines the base level in our region I and can be described by number fluctuations, in which the is independent on . The product is an important parameter related to the base level. The second term presents the curvature of versus in region II and can be described by correlated mobility fluctuations. The curvature of parabola is determined by the product. First, as compared with control device, the reduced level of the embedded SiGe S/D device implies the reduction of or . However, previous literature had reported that SiGe S/D process may lead higher [20, 21]. In other words, it can only be assumed that the reduced mainly contributed to the decreased of SiGe S/D device. The possible mechanism of reduced of SiGe S/D device is explained as follows. The uniaxial compressive stress-induced valence band offset and more holes tend to exist in top band. Therefore, the out-of-plane effective mass () and tunneling barrier height for holes () of SiGe S/D device are both larger than those of control one. As shown in Figure 5, an observed smaller gate current density () in SiGe S/D device confirmed the strain-induced increased and . The is also related to and by [19, 20] where is reduced Planck’s constant. It suggests that strain-increased and bring a smaller in SiGe S/D device. The relation between the trap depth () in insulator and can be revealed according to an equation as . The RTN measurement is a useful tool for probing the trap location in MOSFET [24–26]. It will be applied to confirm our observation and assumption of reduced in the 1/ noise measurement. The RTN characteristics of both devices as a function of the time show themselves in the form of switching events between two states (not shown here). These switching events are attributed to trapping/detrapping caused by an individual interface defect. The times in the high- and low-current states correspond to carrier capture and emission, respectively. The extracted mean capture time () and mean emission time constant () versus () are both presented in Figure 6. It can be found that the SiGe S/D device has the lower values of and and the weak dependence of on , indicating that the trap position is closer to the insulator/semiconductor interface. Figure 7 shows the dependence of / on () for both devices. From the data obtained for ln(/) dependence on gate voltage, the position of the trap into the oxide () is determined using (3) as follows [14, 25]: where is the oxide thickness, and is the Boltzmann constant. As expectation, the extracted is 1.68 nm and 1.14 nm for the control device and the SiGe S/D device, respectively. The reduced in SiGe S/D device is in well agreement on the analysis of 1/ noise (i.e., reduced ) and can be ascribed to the strain-induced higher for hole. Therefore, though the gate dielectric quality may be degraded by the SiGe S/D process, the traps far away from insulator/semiconductor interface cannot act for capturing carriers, thanks to the reduced , which stemmed from uniaxial compressive strain increasing and . Consequently, the improvement of level was observed. On the other hand, in region II, the smaller curvature of of SiGe S/D device indicates the product of is smaller than that of control device, which can be attributed to the strain-induced lower carrier scattering and higher hole mobility at the same time [27, 28]. However, it should be noted that the 1/ performance of our HK pMOSFETs will be probably worse than counterparts with traditional SiO2 insulator . This is owing to the complexity of HK process that led to the higher volume trap densities in gate stacks .
In this paper, we have investigated the effect of compressive strain on low-frequency noise in HK pMOSFET. Through RTN measurement, we found that the HK pMOSFET with the embedded SiGe S/D has a shorter distance of the oxide trap position from the insulator/semiconductor interface. This is ascribed to the higher and smaller for hole stemmed from uniaxial compressive strain-induced bandgap offset. As a result, the improvement of 1/ noise is observed. It is clear that the better performance of low-frequency noise in HK MOSFET device with strain technologies can be expected.
Conflict of Interests
The authors declare that there is no conflict of interests regarding the publication of this paper.
The authors would like to thank the Advanced Optoelectronic Technology Center of NCKU for the financial support under Contract HUA103-3-15-051, the National Science Council of Taiwan for the financial support under Contract numbers NSC102-2221-E-006-259 and NSC102-2221-E-230-015, the Bureau of Energy, Ministry of Economic Affairs of Taiwan for the financial support under Contract number 102-E0603, and UMC staffs for their helpful support.
- Y. Nemirovsky, I. Brouk, and C. G. Jakobson, “1/f noise in CMOS transistors for analog applications,” IEEE Transactions on Electron Devices, vol. 48, no. 5, pp. 921–927, 2001.
- Y. Yasuda and C. Hu, “Effect of fluorine incorporation on 1/f noise of HfSiON FETs for future mixed-signal CMOS,” in Proceedings of the International Electron Devices Meeting (IEDM '06), pp. 1–4, 2006.
- K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, “Unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors,” IEEE Transactions on Electron Devices, vol. 37, no. 3, pp. 654–665, 1990.
- L. K. J. Vandamme, X. Li, and D. Rigaud, “1/f noise in MOS devices, mobility or number fluctuations?” IEEE Transactions on Electron Devices, vol. 41, no. 11, pp. 1936–1945, 1994.
- G. Ghibaudo and T. Boutchacha, “Electrical noise and RTS fluctuations in advanced CMOS devices,” Microelectronics Reliability, vol. 42, no. 4-5, pp. 573–582, 2002.
- L. K. J. Vandamme and F. N. Hooge, “What do we certainly know about 1/f noise in MOSTs?” IEEE Transactions on Electron Devices, vol. 55, no. 11, pp. 3070–3085, 2008.
- C. Hu, “Device challenges and opportunities,” Dig. Tech. Pap. Symp. VLSI Technology, p. 4, 2004.
- T.-J. Wang, C.-H. Ko, H.-N. Lin et al., “Investigation of metallized source/drain extension for high-performance strained NMOSFETs,” IEEE Transactions on Electron Devices, vol. 55, no. 11, pp. 3221–3226, 2008.
- S. E. Thompson, G. Sun, Y. S. Choi, and T. Nishida, “Uniaxial-process-induced Strained-Si: extending the CMOS roadmap,” IEEE Transactions on Electron Devices, vol. 53, no. 5, pp. 1010–1020, 2006.
- E. Simoen, P. Verheyen, A. Shickova, R. Loo, and C. Claeys, “On the low-frequency noise of pMOSFETs with embedded SiGe source/drain and fully silicided metal gate,” IEEE Electron Device Letters, vol. 28, no. 11, pp. 987–989, 2007.
- C. W. Kuo, S. L. Wu, S. J. Chang, H. Y. Lin, Y. P. Wang, and S. C. Hung, “Investigation of interface characteristics in strained-Si nMOSFETs,” Solid-State Electronics, vol. 53, no. 8, pp. 897–900, 2009.
- B. C. Wang, S. L. Wu, C. W. Huang et al., “Correlation between random telegraph noise and 1/f noise parameters in 28-nm pMOSFETs with tip-shaped SiGe source/drain,” IEEE Electron Device Letters, vol. 33, no. 7, pp. 928–930, 2012.
- H.-S. Jung, J.-H. Lee, S. K. Han et al., “A highly manufacturable MIPS (Metal Inserted Poly-Si Stack) technology with novel threshold voltage control,” in Proceedings of the Symposium on VLSI Technology, pp. 232–233, June 2005.
- B. C. Wang, S. L. Wu, C. W. Huang et al., “Characterization of oxide tarps in 28nm p-type metal-oxide-semiconductor field-effect transistors with tip-shaped SiGe source/drain based on random telegraph noise,” Japanese Journal of Applied Physics, vol. 51, Article ID 02BC11, 2012.
- L.-Å. Ragnarsson, Z. Li, J. Tseng et al., “Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization,” in Proceedings of the International Electron Devices Meeting (IEDM '09), pp. 1–4, December 2009.
- J. K. Schaeffer, S. B. Samavedam, D. C. Gilmer et al., “Physical and electrical properties of metal gate electrodes on HfO2 gate dielectrics,” Journal of Vacuum Science and Technology B, vol. 21, no. 1, pp. 11–17, 2003.
- J. R. Hauser and K. Ahmed, “Characterization of ultra-thin oxides using electrical C-V and I-V measurements,” in Proceedings of the International Conference on Characterization and Metrology for ULSI Technology, p. 235, 1998.
- P. C. Huang, S. L. Wu, S. J. Chang et al., “Characteristics of Si/SiO2 interface properties for CMOS fabricated on hybrid orientation substrate using Amorphization/Templated Recrystallization (ATR) method,” IEEE Transactions on Electron Devices, vol. 58, no. 6, pp. 1635–1642, 2011.
- C. W. Kuo, S. L. Wu, S. J. Chang, Y. T. Huang, Y. C. Cheng, and O. Cheng, “Impact of stress-memorization technique induced-tensile strain on low frequency noise in n-channel metal-oxide-semiconductor transistors,” Applied Physics Letters, vol. 97, no. 12, Article ID 123501, 2010.
- J. J. Y. Kuo, W. P. N. Chen, and P. Su, “Impact of uniaxial strain on low-frequency noise in nanoscale PMOSFETs,” IEEE Electron Device Letters, vol. 30, no. 6, pp. 672–674, 2009.
- C. Y. Cheng, Y. K. Fang, J. C. Hsieh et al., “Investigation and localization of the SiGe source/drain (S/D) strain-induced defects in PMOSFET with 45-nm CMOS technology,” IEEE Electron Device Letters, vol. 28, no. 5, pp. 408–411, 2007.
- X. Yang, Y. Choi, T. Nishida, and S. E. Thompson, “Gate direct tunneling currents in uniaxial stressed MOSFETs,” in Proceedings of the International Workshop on Electron Dev and Semiconductor Technology, pp. 149–152, 2007.
- M. V. Haartman and M. Östling, Low-Frequency Noise in Advanced MOS Devices, Springer, Heidelberg, Germany, 2007.
- H. F. Chiu, S. L. Wu, Y. S. Chang et al., “Low surface traps induced noise ZrZnO thin-film transistor using field-plate metal technology,” Japanese Journal of Applied Physics, vol. 52, no. 9, Article ID 04CC22, 2013.
- B. C. Wang, S. L. Wu, Y. Y. Lu et al., “Characterization of oxide traps in 28nm n-type metal-oxide-semiconductor field-effect transistors with different uniaxial tensile stresses utilizing Random telegraph noise,” Japanese Journal of Applied Physics, vol. 52, Article ID 04CC24, 2013.
- S. C. Tsai, S. L. Wu, P. C. Huang et al., “Investigation of Trap Properties of Hf0.83Zr0.17O2 High-k Gate Stack pMOSFETs by Low-frequency (1/f) Noise and RTN Analyses,” in International Workshop on Dielectric Thin Films for Future Electron Devices Science and Technology, p. 87, 2013.
- V. Vartanian, S. Zollner, A. V.-Y. Thean et al., “Metrology challenges for 45-nm strained-Si device technology,” IEEE Transactions on Semiconductor Manufacturing, vol. 19, no. 4, pp. 381–388, 2006.
- S. I. Takagi, J. Koga, and A. Toriumi, “Subband structure engineering for processing-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs,” in Proceedings of the International Electron Devices Meeting (IEDM '97), p. 219, 1997.
- P. Srinivasan, E. Simoen, L. Pantisano, C. Claeys, and D. Misra, “Low-frequency (1f) noise performance of n- and p-MOSFETs with poly-SiHf-based gate dielectrics,” Journal of the Electrochemical Society, vol. 153, no. 4, pp. G324–G329, 2006.
Copyright © 2014 Shih-Chang Tsai et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.