Abstract
Arithmetic and logical unit (ALU) are the core operational programmable logic block in microprocessors, microcontrollers, and real-time-integrated circuits. The conventional ALUs were developed using complementary metal oxide semiconductor (CMOS) technology, which resulted in excessive power consumptions, path delays, and number of transistors. Therefore, this article focuses on the design and development of hybrid delay-controlled reconfigurable ALU (DCR-ALU) using field-effect transistor (FinFET) and graphene nanoribbon field-effect transistor (GnrFET) technologies. Initially, a novel carry output predictable full adder (COPFA) and carry input selectable full adders (CISFA) are developed using multiplexer selection logic; then, delay-controlled hybrid adder (DCHA) and delay-controlled hybrid subtractor (DCHS) are developed using these full adders. In addition, a unified delay-controlled hybrid adder and subtractor (DCHAS) is developed by combining these DCHA and DCHS. Further, a delay controller array multiplier (DCAM) also developed using DCHA modules. Finally, DCR-ALU is developed by adopting the DCHAS, DCAM, and logical operations. The obtained simulation results shows that the proposed nanotechnology-based models outperformed the conventional adders and subtractors in terms of area, power, and delay reduction.
1. Introduction
Recent years, the digital circuitry needs the decrease of area and power by optimizing the time with improving performance in speed. The fundamental digital circuits consist of adders and multipliers as their building blocks. Further, these are generally utilized as various hardware blocks in DSP and ALU frameworks [1]. In DSP, it incorporates refinement and digital filtering like digital communications, spectral analysis, FFT, and DFT. In view of the activity of adder, the power utilization execution relies upon it. In VLSI industry [2], the segments of convenient electronics have quick development for the circuits of low control math. The proficient structure of the power and area utilization with an information path high speed model is a research area to decorate. Through the adder, the speed is constrained according to the time necessity for carry propagation in the digital adders [3]. The situations of every bit are created successively in a steady progression in an adder basic and proliferate a carry into the following position. Many high-performance systems, such as microprocessors, DSP, digital communications, and spectrum analysis, rely on ALUs. The performance of a system is governed by the multiplier’s performance, as it is the system’s most space-consuming and slowest component. As a result, maximizing the multiplier’s [4] speed and area is a crucial design consideration. Since the area and speed are opposing restrictions, several methods and designs have been created to provide a better trade-off between the two. Furthermore, due to the scenario of many DSP applications are aimed at portable, both battery-operated systems and power dissipation are also a significant design limitation. The ALUs are the major building block in every IC, which is utilized widely in various VLSI systems such as specific application of microprocessors and DSP architectures [5]. Further, the ALU performs the logical operations, additions, and multiplications, respectively. The key task of addition is adding the two binary numbers; it is the basis of several useful functions such as division, multiplication, and subtraction and addresses calculation [6], etc. In critical path, adder is a part of most of these systems which regulates the systems’ complete performance. The performance enhancing of the ALU cell (the binary adder building block) is an important goal. Recently, VLSI systems are developing with low power and have occurred as extremely in request due to the development of technologies in computation and communication of mobile. But there is a restricted power offered for the mobile systems. Full adder (FA) is the simple building blocks of various digital VLSI circuits. Some modifications have been done in concern to its structure from its invention. In submicron [7] and deep submicron technologies, the motivation of the VLSI designers is to reduce the static and dynamic power consumption in VLSI ICs. When aiming about the energy efficient arithmetic circuits inside the processors, there is a need for obtaining an energy efficient ALU architecture. To design an energy efficient ALU, which is to be utilized in higher-order adders, one of the necessary parameters is the reduction in total power consumption. This will increase the switching of the logic level signal in all the internal as well as external loads of each subcircuits in arithmetic units which leads to large dynamic power consumption [8]. Hence, the reduction in dynamic power consumption is the most significant factor in improving the energy efficiency in arithmetic building blocks. The rise in leakage current inside the discrete devices fabricated in VLSI IC leads to considerable increase in static power consumption [9]. In order to design an energy efficient ALU cell, one has to concentrate in achieving the reduction in both static and dynamic power consumption. This is evident with the following discussion on power dissipation in CMOS-based circuits.
Recently, FinFET, GnrFET, carbon nanotube FET (CntFET), and RibbonFET are widely using in variety applications for area, power, and delay improvement performance. These advanced FET models are developed by modifying the processing parameters (such as size, thickness, temperature, current, voltage levels, materials of fabrication, gate oxidation, source, and drain divisions, introducing extra terminals) of different layers. Thus, this work considered the FinFET and GnrFET models for development of various arithmetical operations. The major contributions of this work are illustrated as follows:
Initially, modified full adder (MFA) is developed with 10 transistors using multiplexer selection logics. Then, CISFA and COPFA are developed by changing the carry input and carry out operations of MFA.
Further, 4-bit DCHA, DCHS, and DCHAS are developed using MFA, CISFA, and COPFA modules, where DCHS is developed by using two complementation addition properties with DCHA as building block.
Then, 4-bit DCHA, DCHS, and DCHAS blocks are extended with reconfigurable properties, which formed the N-bit implementations of delay-controlled reconfigurable hybrid adder (DCRHA), delay-controlled reconfigurable hybrid subtractor (DCRHS), and delay-controlled reconfigurable hybrid adder subtractor (DCRHAS).
In addition, 4-bit DCAM is developed by using DCHA modules and extended with N-bit delay-controlled reconfigurable array (DCRAM).
Finally. DCR-ALU is developed by using DCRHAS, DCRAM, and logical operations using FinFET and GnrFET technologies. The simulation results show that the proposed models are outperformed in terms of area, power, and delay reduction as compared to conventional adders and subtractors.
Rest of the paper is contributed as follows: Section 2 deals with the related work with problems. Section 3 deals with preliminaries of the proposed models. Section 4 deals with the proposed method. Section 5 deals with simulation results and discussions. Section 6 concludes with future scope.
2. Related Work
This section gives the detailed survey of various adders developed over the past few years. The survey is mainly focusing on analysis of hybrid adders. In [9], the authors developed the approximate adders exhibits with slow speed of compact design but carry look ahead performed faster and consumed more area. Radiation-hardened majority-based magnetic full adder (RHMFA) [10] is designed and performed in this addition process of increasing speed. In analysis of approximate adders, utilizing FinFET shows that the speed of the approximate adders is almost double than the conventional RCA.
In [11], the authors developed the Hybrid FinFET Full adder (HFFA) and Hybrid FinFET adder (HFA) design for video and image processing applications. It exhibits the gate depth in the structure of adder and implemented dual RCA with the input 0 and 1, respectively. Further, Imprecise Minority-Based CNFET Full Adder (IMC-FA) and Imprecise Minority-Based CNFET Adder (IMCA) work with efficient and simple process of significantly modification of gate level and the parameter reduction in conventional HFFA [12]. Further, IMCA is an optimization process in the constraints of VLSI designs, respectively. To overcome the area, power, and delay consumption issues in 4-bit, 8-bit CNTFET Ternary Full adder (CTFA) and CNTFET Ternary adder (CTA) without utilizing Mux and utilizing approximate adders is developed in [13] and simulations resulted in better performance for modified designs as compared to state of art approaches. The ternary half adder and 1-trit multiplier architecture have been developed [14] and evaluated the performances of the design in terms of area, power, and delay.
In [15], the authors developed the PTL-based subtractor (PTLS) with the gate-level modifications, which required less gates to perform the operation in the proposed work. It provides area reduction and the total power. The result analysis shows the better performances of the circuit and faster than the others. In this way, MTCMOS subtractor (MTCMOSS) [16] makes efficient and simple way to process the VLSI hardware implementations. The mobile industry is growing rapidly not only because of arithmetic unit but also with the arithmetic units of less power and area. A simple and efficient modification of gate level makes the reduction in power, area, and delay in Trit Unbalanced Ternary Subtractor (TUTS) [17]. Based on the modifications of CSLA, the performances were compared with other adders. By the BEC modification instead of MFA [18] chain, the logic converter provides the circuit with slight changes of delay. The fast process performances of TUTS are utilized for arithmetic functions in data processing processors.
In [19], the authors developed the gating-aware energy adders and subtractors (GAEAS) for power utilization that has transformation. For the reduction of circuit consumption, BEC is utilized in the modified quantum adders instead of CSLA and RCA with increasing the delay slightly. In [20], the authors proposed the low error efficient approximate FinFET-based Hybrid Adder/Subtractor Circuit (FHAS), which is linear proportional of delay performed with -bit, so highest delay process is performed by these adders. Normally, it provides faster results with more delay process than the other adders. It provided because of large number of logic gates and fan-in. In [21], the authors proposed CNTFET-based adder and subtractor (CNTFET-AS), which exhibits high speed with compact design but consumes more area. Also, CNTFET is accessible with low-power multipliers. The simulation results shown that it resulted in better performance as compared to the FinFET-based adders [22]. In [23], the authors developed the multioperative reversible adder and subtractor (MRAS), which can be used in the design of high-performance modules [24] like multiple bit adders, multipliers, multiplexers, subtractors, comparators, and registers. The advancement in fabrication nanotechnology [25] with the shrinking device sizes has allowed for placement of nearly two billion transistors on Intel’s advanced processor.
In [26], the authors developed the 14 nm FinFET technology-based 8-bit Dadda multiplier (FDM) using approximate 4 : 2 compressors. The carry propagate adders are designed with a 4 : 2 compressor to reduce the height of the partial product rows. Further, CNTFET-based vedic mathematics processor (CVMP) [27] is developed to reduce the power complexities presented in the FDM, which performs additions, multipliers, multiply and accumulations, and DWT operations. The maximum height of the partial product was reduced by one unit. This was achieved through the pipelining of the multiplier by optimization of the array reduction stage. In [28], the authors developed the Majority-Based Imprecise Multiplier (MBIM) with 7 nm FinFET. The MBIM adopted the advanced quantum dot cellular automata for generalization of majority logic formulations. The partial product reductions were achieved through the hybrid compressors with majority logic gates. Further, FinFET-based Energy Efficient Pass Transistor Adiabatic Logic (EEPAL) [29] was introduced to develop the Carry Save Multiplier. But this method consumes the high computational complexity in terms of delay. In [30], the authors developed the area-efficient FinFET-based approximate multiplier methodology with low voltage with least current consumption circuits. These were implemented for a current feed operational EETM and the current conveyor. Then, FinFET-based discrete wavelet transform (FDWT) [31] was developed by using reversable logic gates. The comparison has revealed that this method of FinFET design could reduce the area by almost 50% of the smallest area.
In [32], the authors developed high-speed 8-bit ALU (HS-ALU) using 18 nm FinFET technology which is based on the kogge stone additions and Dadda multiplier. It is one of the most vividly encountered operations across a majority of the real-time DSP solutions but consumed higher power. Further, N-bit ALU [33] is developed by using 18 nm FinFET technology, which mainly implies function of additions and designs relied the considerable speed as it is one of the performance metrics and digital circuits with high-speed performance has always gained significant importance. This method is suffering with the high computational complexity. In [34], the authors developed the 32 nm-FinFET-based 4-bit ALU (FALU-32) developed using array multipliers, carry save additions. The power consumption in the case of the FALU-32 circuit is to be mitigated either for two distinct reasons as to mitigate the heat dissipation to support significant volumes of functions that are integral to handling the IC. Further, sub-10 nm gate length-based Schottky-barrier FinFET (SB-FinFET) [35] was developed to reduce the power consumption problems presented in basic FinFET technology. Further, 1-bit ALU is developed by using SB-FinFET technology; however, this method is suffering with the fabrication issues. Then, hybrid pin-transfer torque-magnetic tunnel junction (STT-MTJ) and hybrid tunnel FET (TFET) [36] are developed to reduce the mutual problems presented in conventional GnrFET, FinFET, and CNTFET technologies. Then, 1-bit magnetic ALU (MALU) is developed by using STT-MTJ and TFET technologies, where STT-MTJ resulted in reduced area and delay metrics.
3. Preliminaries
The design and development of full adders are critical because they are the fundamental building blocks of all integrated circuits. Therefore, the design of full adders must be done with care because of their importance. Basic CMOS technology-based full adder is utilizing the greater energy, area, delay, and power consumption. So, the GnrFET and FinFET technologies serve as an alternate technology to the basic CMOS technology, which is characterized by low resource consumption. This work implemented novel three different types of full adders for performing addition and subtraction operations. They are MFA with 10 transistors, COPFA with 12 transistors, and CISFA with 12 transistors, respectively. All the three designs contain equal number of PMOS and NMOS transistors, which allows for the introduction of the equilibrium state in three models, allowing for the control and synchronization of the unbiased electron-hole pair. Furthermore, this equilibrium condition ensures that the ideal power consumption is maintained while simultaneously improving energy efficiency.
3.1. MFA
Figure 1 shows the block diagram of MFA, which contains two multiplexers for sum and carry out generations. Here, is applied as selection input to the MUX21, and it generates the sum output based on data selection logic between XOR and XNOR outcomes. Finally, sum output of MFA is generated as follows:
Further, XNOR of inputs is applied as selection input to the MUX21-A, and it generates the carry output based on data selection logic. Finally, carry output of MFA is generated as follows:
Figure 2 shows the FinFET-based transistor level architecture of the proposed MFA, which contains five PMOS-FinFETs and five NMOS-FinFETs. Initially, input is applied to the gate terminal of P1 and N1 FinFETs, which functions as inverter and generates the outcome . Further, and input are applied to gate terminal of P2 and N2 FinFETs, which functions as XOR gate and generates output as . Further, is also applied to the gate terminal of P3 and N3 FinFETs, which act as inverter and generates the output as . Then, is applied as input to gate terminal to the gate terminal of P4 and N4 FinFETs, which acts as MUX21 with and as data inputs, so sum output is generated. Finally, was generated from MUX21 applied as input to gate terminal of P5 and N5 FinFETs, which acts as MUX21, so carry output is generated.
3.2. CISFA
The major advantage of CISFA is that it has the potential capability to select the carry inputs. Generally, the complexity of addition process purely depends on carry generation and forwarding nature. So, the fast operation of full adders can be effectively performed by minimizing the computations through different carry inputs. The CISFA module considers the selectable extra carry input (), which is different from original carry input ().
Figure 3 shows the block diagram of CISFA, which is implemented from the fundamentals of MFA by introducing the extra OR gate. Initially, and applied as input to MUX21, which is used to select the two carry inputs. Here, if both inputs and are equal, then MUX21-A generates the output as , and if inputs and are not equal, then MUX21-A generates the output as . The operation of MUX21-A is illustrated as follows:
Then, output of MUX21-A () is applied as selection input to the MUX21-A, which generates the sum output based on XOR-XNOR selection logic. Finally, sum of CISFA is generated as follows:
Further, XNOR of inputs is applied as selection input to the MUX21-A, and it generates the carry output based on data selection logic. Finally, carry output of CISFA is generated as follows:
Figure 4 shows the FinFET layout of CISFA, which contains 6 number of PMOS-FinFETs and 6 number of NMOS-FinFETs. Initially, input is applied to the gate terminal of P1 and N1 FinFETs, which functions as inverter and generates the outcome . Further, and input are applied to gate terminal of P2 and N2 FinFETs, which functions as XOR gate and generates output as In addition, is applied to gate terminal of P3 and N3 FinFETs, which acts as MUX21-A with and as data inputs. Further, is also applied to the gate terminal of P4 and N4 FinFETs, which act as inverter and generates the output as . Then, generated from MUX21-A is applied as input to gate terminal of P5 and N5 FinFETs, which acts as MUX21-B with and as data inputs, so sum output is generated. Finally, generated from MUX21-B is applied as input to gate terminal of P6 and N6 FinFETs, which acts as MUX21-C, so carry output is generated.
3.3. COPFA
The major advantage of COPFA is that it predicts two carry outputs such as carry output () and predictable carry output (). These carry outputs are used as inputs for the CISFA module, which can be used to fast switching of data. Figure 5 shows the block diagram of COPFA, which is implemented by replacing XOR gate with XOR-AN module. This module generates both XOR and AND outputs, where AND output is the temporary carry output.
In most scenarios, is generated when two or more numbers of ones available in input data, so this temporary carry out will check the availability of ones and generates the respectively. Figure 6 shows the FinFET layout of COPFA, which contains 6 number of PMOS-FinFETs and 6 number of NMOS-FinFETs. It is also acts similar like MFA with extra AND operation.
4. Proposed DCR-ALU Method
ALUs are the basic building in every integrated circuit, and they decide the performance of various applications. Thus, the optimal design of adders and subtractors will improve the performance of microprocessors and microcontrollers. This section deals with the detailed analysis of implementation DCR-ALU, which is developed by using DCRHA, DCRHS, DCRHAS, and DCRAM, respectively. Further, these adders and subtractors are developed by using-by-using MFA, COPFA, and CISFA modules (mentioned in Section 3). Figure 7 shows the N-bit implementation of the proposed DCR-ALU, which consumes the low area, power, and delay properties as they are implemented by using advanced full adders. Here, are N-bit inputs, is the selection line with three inputs, and OUT is the final ALU output. Further, based on selection combinations, ALU will perform the different operations. Table 1 presents the detailed operations for each selection combination of the proposed DCR-ALU.
4.1. DCRHA
The delay problems generated in the conventional adders are overcome by introducing CISFA-COPFA combination. The MFA and MUX21 of basic adders are replaced by CISFA-COPFA combination, which significantly reduces the area, power, and delay as compared to other approaches. Figure 8 shows the block diagram of DCHA. It reduces the problems generated in the SRHA by employing the high-speed carry propagation (HSCP) and regular-speed carry propagation (RSCP) paths. Here, HSCP is the low delay consumption path, RSCP is the high delay consumption path. Further, the DCHA is developed by replacing the intermediate MFA stages of SRHA with COPFA and CISFA modules.
The 4-bit DCHA totally contains 44 number of FinFETs. The detailed operation of 4-bit DCHA is illustrated as follows:
Step 1. Initially, and are applied as input to the MFA-1 and it generates as output signals.
Step 2. Apply and variables as inputs to COPFA, which generates the as regular carry out and as predicated carry out. Here, is generated fast by analyzing the intermediate carries as compared to .
Step 3. Apply , , and variables as inputs to CISFA, and it generates as output signals. This module has the capacity to generate carry output by selecting high-speed input data levels. Based on the accurate sum generation situations, accurate path is selected. Usually, the RSCP path contains the generalized carry propagations, and HSCP path contains propagation carry from predicted outcome to selectable input.
Step 4. Finally, and are applied as input to the MFA, and it generates final outputs , .
The proposed 4-bit DCHA contains the “reconfiguration block,” which is formed by the combination of CISFA and COPFA modules. This reconfigurable block is used to develop the N-bit DCRHA by repeating the reconfiguration blocks multiple times. Further, the number of reconfiguration blocks is decided by length of N-bit DCRHA. For N-bit length of DCRHA, numbers of reconfiguration blocks are used. Further, the number of transistors in the N-bit DCRHA is, respectively.
Figure 9 shows the block diagram of N-bit DCRHA, and its operation is illustrated as follows:
Step 1. Initially, and are applied as input to the MFA-1, and it generates , -based output signals.
Step 2. Apply and variables as inputs to COPFA, which generates the . Apply , , and variables as inputs to CISFA, and it generates as output signals.
Step 3. The process of reconfigurable blocks is repeated for other inputs, and the number of reconfigurable blocks is depending on factor .
Step 4. Finally, , , and are applied as inputs to the MFA, and it generates final outputs .
4.2. DCRHS
This section gives the detailed analysis of hybrid subtractors, which are developed by performing the twos complement addition process. Therefore, there is no special requirement of full subtractors for performing subtraction operation.
Figure 10 shows the block diagram of DCHS, and it is developed by performing the twos complement operation on DCHA. The 4-bit DCHS totally contains 52 () number of FinFETs; here 8 extra FinFETs are used for four inverters. The detailed operation of 4-bit DCHS is illustrated as follows. Initially, input is applied to the inverter, which generates the as output. Then, and are applied as input to the MFA, but it acts as full subtractor and generates and as output signals. Apply and variables as inputs to COPFA, which generates the as regular borrow out and as predicated borrow out. Here, is generated fast by analyzing the intermediate borrows as compared to . Apply , , and variables as inputs to CISFA, and it generates as output signals. Finally, and are applied as input to the MFA, and it generates final outputs .
Figure 11 shows the block diagram of N-bit DCRHS, and its operation is illustrated as follows, initially, and are applied as input to the MFA and it generates based output signals. Apply and variables as inputs to COPFA, which generates the . Apply , , and variables as inputs to CISFA, and it generates as output signals. The process of reconfigurable blocks is repeated for number of times and generates multiple difference, borrow outputs. Finally, and are applied as input to the MFA and it generates final outputs .
4.3. DCRHAS
Figure 12 shows the block diagram of 4-bit DCHAS, and it is developed by performing the twos complement operation with mode selection properties. Figure 13 shows the block diagram of N-bit DCRHAS. The DCHAS contains pin, which is used to select addition and subtraction operations. Further, if is zero, then DCHAS acts as DCHA, because XOR operation between , results output the same as only. In this case, sum-difference output (SD) signal acts as and carry-borrow (CB) output signal acts as . In addition, if is one, then DCHAS act as DCHS, because XOR operation between , results output as , respectively. This complemented output is useful for twos complement-based addition process to generate the end difference outcome. In this case, sum-difference output (SD) signal acts as and carry-borrow (CB) output signal acts as .
4.4. DCRAM
This section gives the detailed analysis of delay controlled reconfigurable array multiplier (DCRAM), which is developed by using DCRHA. Figure 14 shows the architecture of DCAM, which is developed by using FinFET/GnrFET-based AND gates and 4-bit DCRHAs. Initially, 4-bit inputs such as and are applied to AND gates, which generates the partial products.
Here, represents the partial products, represents the bit position of input , and represents the bit position of input . In the scenario of 4-bit DCAM, values of and are ranged from 0 to 3, respectively. For an instance, represents the operation between and .Further, these partial products are applied to multistage 4-bit DCRHA, which generates the final multiplier output bits. Table 2 presents the detailed operation of 4-bit DCAM.
The operation of 4-bit DCAM is extended with N-bits with reconfigurable properties and generated as N-bit DCRAM. Figure 15 presents the architecture of N-bit DCRAM, which is developed by using FinFET/GnrFET-based AND gates and N-bit DCRHAs. Here, inputs are ranged from to such as {} and , respectively. Further, develop the partial products using FinFET/GnrFET-based AND gates. Here, N-bit DCAM is capable of developing the number of partial products. Further, The N-bit DCAM contains (N-1) number of N-bit DCRHAs, where the output of one adder is applied is input to next stage. Then, apply these partial products to N-bit DCRHAs and reduce the partial products with stage-by-stage multiplication, which resulted in final product bits. Table 3 presents the detailed operation of N-bit DCRAM.
5. Results and Discussion
This section provides a full examination of simulation results obtained using a variety of parameters, which may be used to demonstrate the efficiency of the proposed research. On top of that, all of the planned tasks have been implemented and simulated, and their parameters have been determined using the HSpice tool on both the FinFET and GnrFET technology platforms. Also included is a full analysis of the many simulation parameters that were utilized in the design and development of the proposed work using the H-SPICE tool, which is shown in Table 4.
5.1. Performance Evaluation
This work considers the multiple metrics to evaluate the performance of the proposed models and comparison with state of art approaches. They are average power consumption (APC), sum rise delay (SRD), sum fall delay (SFD), carry output rise delay (CORD), carry output fall delay (COFD), static noise margin (SNM), total energy consumption (TEC), static power consumption (SPC), total current (TC), and propagation delay (PD). Table 5 compares the 7 nm based FinFET and 22 nm based GnrFET performances for various proposed modules such as DCHA, DCHS, DCHAS, DCAM, and DCR-ALU. Further, the FinFET technology resulted in superior performance as compared GnrFET technology for all the proposed models.
Table 6 compares the performance of the proposed CISFA with various state of art models like RHMFA [10], HFFA [11], IMC-FA [12], CTFA [13], and MFA [18]. From the simulations, it is observed that the proposed CISFA resulted in superior performance, because the CISFA utilizes the advanced path selection mechanisms. Further, the conventional methods suffering with the more power consumptions due to a greater number of transistors.
Table 7 compares the performance of the proposed DCHA with various state of art adders like HFA [11], IMCA [12], CTA [13], and RCA [18]. From the simulations, it is observed that the proposed DCHA resulted in superior performance, because the CPHA utilizes the COPFA-based path forwarding properties. Table 8 compares the performance of the proposed DCHS with various state of art subtractors like PTLS [15], MTCMOSS [16], and TUTS [17]. From the simulations, it is observed that the proposed DCHS resulted in superior performance, because it performs subtraction using twos complement addition process. Table 9 compares the performance of the proposed DCHAS with various state of art combined adders and subtractors like GAEAS [19], FHAS [20], CNTFET-AS [21], and MRAS [23]. From the simulations, it is observed that the proposed DCHAS resulted in superior performance, because it performs subtraction using twos complement addition process.
Table 10 compares the performance of the proposed DCAM with various state of art multipliers like FDM [26], MBIM [28], EEPAL [29], and CVMP [27]. From the simulations, it is observed that the proposed DCAM resulted in superior performance, because it utilizes the delay controller environment for data transfer from one module to another module.
Table 11 compares the performance of the proposed DCR-ALU with various existing ALUs such as HS-ALU [32], FALU-32 [34], SB-FinFET [35], and STT-MTJ [36]. The conventional ALUs are developed by using basic adders, multiplier prototypes, which caused to increase area, delay, and power consumptions. Further, the proposed DCR-ALU utilizes delay intensive paths, which caused to improve the performance.
6. Conclusion
This article implemented the FinFET and GnrFET technology-based DCR-ALU by adopting the DCHA, DCHS, DCHAS, and DCAM modules. Initially, a unified 12 transistor COPFA and CISFA are developed by using multiplexer selection logic with low delay paths. Then, DCHA, DCHS, and DCHAS modules are developed by using COPFA and CISFA, which has the potential capacity to select the low-speed and high-speed carry propagation paths. In addition, DCAM developed with low area properties by using DCHA and FinFET/GnrFET technology-based AND gates. Moreover, all these DCHA, DCHS, DCHAS, and DCAM modules are extended with reconfigurable properties, which are formed as N-bit DCRHA, DCRHS, DCRHAS, and DCFRAM modules. The simulation results demonstrate that the proposed approach outperforms conventional adders and subtractors and consumed a smaller number of transistors, reduced power consumption with path delays. In future, the present work can be extended to compute multiplication and accumulator operations with the proposed hybrid architectures.
Data Availability
The data used to support the findings of this study are included within the article.
Disclosure
The study was performed as a part of the Employment of Salale University, Ethiopia.
Conflicts of Interest
The authors declared that there is no conflict of interest in publication.