Table of Contents [26–50 of 759 articles]

• Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies, M. A. R. Chaudhry, Z. Asad, A. Sprintson, and J. Hu
  Volume 2011 (2011), Article ID 892310, 9 pages
• Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints, Yoni Aizik and Avinoam Kolodny
  Volume 2011 (2011), Article ID 845957, 13 pages
• SoC: A Real Platform for IP Reuse, IP Infringement, and IP Protection, Debasri Saha and Susmita Sur-Kolay
  Volume 2011 (2011), Article ID 731957, 10 pages
• CONTANGO: Integrated Optimization of SoC Clock Networks, Dong-Jin Lee and Igor L. Markov
  Volume 2011 (2011), Article ID 407507, 12 pages
• The Impact of Statistical Leakage Models on Design Yield Estimation, Rouwaida Kanj, Rajiv Joshi, and Sani Nassif
  Volume 2011 (2011), Article ID 471903, 12 pages
• New Considerations for Spectral Classification of Boolean Switching Functions, J. E. Rice, J. C. Muzio, and N. Anderson
  Volume 2011 (2011), Article ID 356137, 9 pages
• Shedding Physical Synthesis Area Bloat, Ying Zhou, Charles J. Alpert, Zhuo Li, Cliff Sze, and Louise H. Trevillyan
  Volume 2011 (2011), Article ID 503025, 10 pages
• Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey, Usha Mehta, Kankar Dasgupta, and Niranjan Devashrayee
  Volume 2011 (2011), Article ID 948926, 7 pages
• Buffer Planning for IP Placement Using Sliced-LFF, Ou He, Sheqin Dong, Jinian Bian, and Satoshi Goto
  Volume 2011 (2011), Article ID 530851, 10 pages
• Table of Contents for Year 2010
• A Cost-Effective 10-Bit D/A Converter for Digital-Input MOEMS Micromirror Actuation, Sergio Saponara, Tommaso Baldetti, and Luca Fanucci
  Volume 2010 (2010), Article ID 169079, 7 pages
• Selected Papers from the Midwest Symposium on Circuits and Systems, Gregory D. Peterson, Ethan Farquhar, and Benjamin Blalock
  Volume 2010 (2010), Article ID 538454, 2 pages
• An Approach for Implementing State Machines with Online Testability, P. K. Lala, A. Mathews, and J. P. Parkerson
  Volume 2010 (2010), Article ID 639747, 7 pages
• Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits, Tooraj Nikoubin, Poona Bahrebar, Sara Pouri, Keivan Navi, and Vaez Iravani
  Volume 2010 (2010), Article ID 264390, 17 pages
• CORDIC Architectures: A Survey, B. Lakshmi and A. S. Dhar
  Volume 2010 (2010), Article ID 794891, 19 pages
• Run-Length-Based Test Data Compression Techniques: How Far from Entropy and Power Bounds?—A Survey, Usha S. Mehta, Kankar S. Dasgupta, and Niranjan M. Devashrayee
  Volume 2010 (2010), Article ID 670476, 9 pages
• Nonlinear Circuit Analysis via Perturbation Methods and Hardware Prototyping, K. Odame and P. E. Hasler
  Volume 2010 (2010), Article ID 687498, 8 pages
• FPGA Implementation of an Amplitude-Modulated Continuous-Wave Ultrasonic Ranger Using Restructured Phase-Locking Scheme, P. Sumathi and P. A. Janakiraman
  Volume 2010 (2010), Article ID 213043, 11 pages
• Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs, Yan Zhu, U-Fat Chio, He-Gong Wei, Sai-Weng Sin, Seng-Pan U, and R. P. Martins
  Volume 2010 (2010), Article ID 706548, 8 pages
• Local Biasing and the Use of Nullator-Norator Pairs in Analog Circuits Designs, Reza Hashemian
  Volume 2010 (2010), Article ID 297083, 12 pages
• Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations, Kumar Yelamarthi and Chien-In Henry Chen
  Volume 2010 (2010), Article ID 230783, 13 pages
• Implementation of Hardware-Accelerated Scalable Parallel Random Number Generators, JunKyu Lee, Gregory D. Peterson, Robert J. Harrison, and Robert J. Hinde
  Volume 2010 (2010), Article ID 930821, 11 pages
• A Pipelined and Parallel Architecture for Quantum Monte Carlo Simulations on FPGAs, Akila Gothandaraman, Gregory D. Peterson, G. Lee Warren, Robert J. Hinde, and Robert J. Harrison
  Volume 2010 (2010), Article ID 946486, 8 pages
• Error Immune Logic for Low-Power Probabilistic Computing, Bo Marr, Jason George, Brian Degnan, David V. Anderson, and Paul Hasler
  Volume 2010 (2010), Article ID 460312, 9 pages
• Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments, Saumil G. Merchant and Gregory D. Peterson
  Volume 2010 (2010), Article ID 251210, 25 pages
• Post-CTS Delay Insertion, Jianchao Lu and Baris Taskin
  Volume 2010 (2010), Article ID 451809, 9 pages