VLSI Design

A 0.6-V to 1-V Audio Modulator in 65 nm CMOS with 90.2 dB SNDR at 0.6-V

Fast and Near-Optimal Timing-Driven Cell Sizing under Cell Area and Leakage Power Constraints Using a Simplified Discrete Network Flow Algorithm

A High-Efficiency Monolithic DC-DC PFM Boost Converter with Parallel Power MOS Technique

Low Complexity Submatrix Divided MMSE Sparse-SQRD Detection for MIMO-OFDM with ESPAR Antenna Receiver

Verification of Mixed-Signal Systems with Affine Arithmetic Assertions

Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL

A High-Speed and Low-Energy-Consumption Processor for SVD-MIMO-OFDM Systems

Discrete Wavelet Transform on Color Picture Interpolation of Digital Still Camera

A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures

Energy-Efficient Hardware Architectures for the Packet Data Convergence Protocol in LTE-Advanced Mobile Terminals

A Graph-Based Approach to Optimal Scan Chain Stitching Using RTL Design Descriptions

Absolute Difference and Low-Power Bus Encoding Method for LCD Digital Display Interfaces

A ±6 ms-Accuracy, 0.68 mm², and 2.21 μW QRS Detection ASIC

A Novel Framework for Applying Multiobjective GA and PSO Based Approaches for Simultaneous Area, Delay, and Power Optimization in High Level Synthesis of Datapaths

Line Search-Based Inverse Lithography Technique for Mask Design

VLSI Design

Table of Contents

Table of Contents

A 0.6-V to 1-V Audio Modulator in 65 nm CMOS with 90.2 dB SNDR at 0.6-V

Fast and Near-Optimal Timing-Driven Cell Sizing under Cell Area and Leakage Power Constraints Using a Simplified Discrete Network Flow Algorithm

A High-Efficiency Monolithic DC-DC PFM Boost Converter with Parallel Power MOS Technique

Low Complexity Submatrix Divided MMSE Sparse-SQRD Detection for MIMO-OFDM with ESPAR Antenna Receiver

Verification of Mixed-Signal Systems with Affine Arithmetic Assertions

Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL

A High-Speed and Low-Energy-Consumption Processor for SVD-MIMO-OFDM Systems

Discrete Wavelet Transform on Color Picture Interpolation of Digital Still Camera

A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures

Energy-Efficient Hardware Architectures for the Packet Data Convergence Protocol in LTE-Advanced Mobile Terminals

A Graph-Based Approach to Optimal Scan Chain Stitching Using RTL Design Descriptions

Absolute Difference and Low-Power Bus Encoding Method for LCD Digital Display Interfaces

A ±6 ms-Accuracy, 0.68 mm², and 2.21 μW QRS Detection ASIC

A Novel Framework for Applying Multiobjective GA and PSO Based Approaches for Simultaneous Area, Delay, and Power Optimization in High Level Synthesis of Datapaths

Line Search-Based Inverse Lithography Technique for Mask Design

VLSI Design

Table of Contents

Table of Contents

A 0.6-V to 1-V Audio Modulator in 65 nm CMOS with 90.2 dB SNDR at 0.6-V

Fast and Near-Optimal Timing-Driven Cell Sizing under Cell Area and Leakage Power Constraints Using a Simplified Discrete Network Flow Algorithm

A High-Efficiency Monolithic DC-DC PFM Boost Converter with Parallel Power MOS Technique

Low Complexity Submatrix Divided MMSE Sparse-SQRD Detection for MIMO-OFDM with ESPAR Antenna Receiver

Verification of Mixed-Signal Systems with Affine Arithmetic Assertions

Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL

A High-Speed and Low-Energy-Consumption Processor for SVD-MIMO-OFDM Systems

Discrete Wavelet Transform on Color Picture Interpolation of Digital Still Camera

A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures

Energy-Efficient Hardware Architectures for the Packet Data Convergence Protocol in LTE-Advanced Mobile Terminals

A Graph-Based Approach to Optimal Scan Chain Stitching Using RTL Design Descriptions

Absolute Difference and Low-Power Bus Encoding Method for LCD Digital Display Interfaces

A ±6 ms-Accuracy, 0.68 mm2, and 2.21 μW QRS Detection ASIC

A Novel Framework for Applying Multiobjective GA and PSO Based Approaches for Simultaneous Area, Delay, and Power Optimization in High Level Synthesis of Datapaths

Line Search-Based Inverse Lithography Technique for Mask Design

A ±6 ms-Accuracy, 0.68 mm², and 2.21 μW QRS Detection ASIC