VLSI Design

High Throughput Pseudorandom Number Generator Based on Variable Argument Unified Hyperchaos

Novel Receiver Architecture for LTE-A Downlink Physical Control Format Indicator Channel with Diversity

VLSI Architectures for Image Interpolation: A Survey

Radix-2^α/4^β Building Blocks for Efficient VLSI’s Higher Radices Butterflies Implementation

Low-Area Wallace Multiplier

Efficient Hardware Trojan Detection with Differential Cascade Voltage Switch Logic

On-Chip Power Minimization Using Serialization-Widening with Frequent Value Encoding

A Self-Reconfigurable Platform for the Implementation of 2D Filterbanks with Real and Complex-Valued Inputs, Outputs, and Filter Coefficients

New Algorithmic Techniques for Complex EDA Problems

Design of Finite Word Length Linear-Phase FIR Filters in the Logarithmic Number System Domain

Advanced VLSI Design Methodologies for Emerging Industrial Multimedia and Communication Applications

A Low-Power Scalable Stream Compute Accelerator for General Matrix Multiply (GEMM)

Improved Quantization Error Compensation Method for Fixed-Width Booth Multipliers

Meta-Algorithms for Scheduling a Chain of Coarse-Grained Tasks on an Array of Reconfigurable FPGAs

A Generic Three-Sided Rearrangeable Switching Network for Polygonal FPGA Design

VLSI Design

Table of Contents

Table of Contents

High Throughput Pseudorandom Number Generator Based on Variable Argument Unified Hyperchaos

Novel Receiver Architecture for LTE-A Downlink Physical Control Format Indicator Channel with Diversity

VLSI Architectures for Image Interpolation: A Survey

Radix-2^α/4^β Building Blocks for Efficient VLSI’s Higher Radices Butterflies Implementation

Low-Area Wallace Multiplier

Efficient Hardware Trojan Detection with Differential Cascade Voltage Switch Logic

On-Chip Power Minimization Using Serialization-Widening with Frequent Value Encoding

A Self-Reconfigurable Platform for the Implementation of 2D Filterbanks with Real and Complex-Valued Inputs, Outputs, and Filter Coefficients

New Algorithmic Techniques for Complex EDA Problems

Design of Finite Word Length Linear-Phase FIR Filters in the Logarithmic Number System Domain

Advanced VLSI Design Methodologies for Emerging Industrial Multimedia and Communication Applications

A Low-Power Scalable Stream Compute Accelerator for General Matrix Multiply (GEMM)

Improved Quantization Error Compensation Method for Fixed-Width Booth Multipliers

Meta-Algorithms for Scheduling a Chain of Coarse-Grained Tasks on an Array of Reconfigurable FPGAs

A Generic Three-Sided Rearrangeable Switching Network for Polygonal FPGA Design

VLSI Design

Table of Contents

Table of Contents

High Throughput Pseudorandom Number Generator Based on Variable Argument Unified Hyperchaos

Novel Receiver Architecture for LTE-A Downlink Physical Control Format Indicator Channel with Diversity

VLSI Architectures for Image Interpolation: A Survey

Radix-2α/4β Building Blocks for Efficient VLSI’s Higher Radices Butterflies Implementation

Low-Area Wallace Multiplier

Efficient Hardware Trojan Detection with Differential Cascade Voltage Switch Logic

On-Chip Power Minimization Using Serialization-Widening with Frequent Value Encoding

A Self-Reconfigurable Platform for the Implementation of 2D Filterbanks with Real and Complex-Valued Inputs, Outputs, and Filter Coefficients

New Algorithmic Techniques for Complex EDA Problems

Design of Finite Word Length Linear-Phase FIR Filters in the Logarithmic Number System Domain

Advanced VLSI Design Methodologies for Emerging Industrial Multimedia and Communication Applications

A Low-Power Scalable Stream Compute Accelerator for General Matrix Multiply (GEMM)

Improved Quantization Error Compensation Method for Fixed-Width Booth Multipliers

Meta-Algorithms for Scheduling a Chain of Coarse-Grained Tasks on an Array of Reconfigurable FPGAs

A Generic Three-Sided Rearrangeable Switching Network for Polygonal FPGA Design

Radix-2^α/4^β Building Blocks for Efficient VLSI’s Higher Radices Butterflies Implementation