VLSI Design

Digital Noise Generator Design Using Inverted 1D Tent Chaotic Map

Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (D/FLL) Architecture

VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards

Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation

Design Space Exploration of Deeply Nested Loop 2D Filtering and 6 Level FSBM Algorithm Mapped onto Systolic Array

Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs

Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time Multimedia Signal Processing

FastRoute: An Efficient and High-Quality Global Router

Point DCT VLSI Architecture for Emerging HEVC Standard

A Systematic Methodology for Reliability Improvements on SoC-Based Software Defined Radio Systems

Flexible LDPC Decoder Architectures

Hardware Design Considerations for Edge-Accelerated Stereo Correspondence Algorithms

Optimized Architecture Using a Novel Subexpression Elimination on Loeffler Algorithm for DCT-Based Image Compression

Design Space of Flexible Multigigabit LDPC Decoders

An Efficient Multi-Core SIMD Implementation for H.264/AVC Encoder

VLSI Design

Table of Contents

Table of Contents

Digital Noise Generator Design Using Inverted 1D Tent Chaotic Map

Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (D/FLL) Architecture

VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards

Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation

Design Space Exploration of Deeply Nested Loop 2D Filtering and 6 Level FSBM Algorithm Mapped onto Systolic Array

Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs

Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time Multimedia Signal Processing

FastRoute: An Efficient and High-Quality Global Router

Point DCT VLSI Architecture for Emerging HEVC Standard

A Systematic Methodology for Reliability Improvements on SoC-Based Software Defined Radio Systems

Flexible LDPC Decoder Architectures

Hardware Design Considerations for Edge-Accelerated Stereo Correspondence Algorithms

Optimized Architecture Using a Novel Subexpression Elimination on Loeffler Algorithm for DCT-Based Image Compression

Design Space of Flexible Multigigabit LDPC Decoders

An Efficient Multi-Core SIMD Implementation for H.264/AVC Encoder