A variation-tolerant low-power source-synchronous multicycle (SSMC ) interconnect 
	scheme is proposed. This scheme is scalable and suitable for transferring data across
	 different clock domains such as those in &#8220;many-core&#8221; SoCs and in 
	 3D-ICs. SSMC replaces intermediate flip-flops by a source-synchronous synchronization 
	 scheme. Removing the intermediate flip-flops in the SSMC scheme enables better averaging
	 of delay variations across the whole interconnect, which reduces bit-rate degradation due to
	 within-die WID process variations. Monte Carlo circuit simulations show that SSMC eliminates 
	 <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mn>90</mml:mn><mml:mi>&#x0025;</mml:mi></mml:mrow></mml:math> of the variation-induced performance degradation in a 6-cycle 9&#8201;mm-long 
16-bit conventional bus.
The proposed multicycle bus scheme also leads to significant energy savings due to eliminating 
the power-hungry flip-flops and efficiently designing the source synchronization 
overhead. Moreover, eliminating intermediate flip-flops avoids the timing overhead of the setup 
time, the flip-flop delay, and the single-cycle clock jitter. This delay slack can then be translated into
 further energy savings by downsizing the repeaters. The significant delay jitter due to capacitive 
 coupling has been addressed and solutions are put forward to alleviate it. Circuit simulations in 
 a &#8201;65-nm process environment indicate that energy savings up to <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mn>20</mml:mn><mml:mi>&#x0025;</mml:mi></mml:mrow></mml:math> are achievable for a 6-cycle 9&#8201;mm long 16-bit bus.

Maged  Ghoneima

Yehea  Ismail

Muhammad  Khellah

Vivek  De

Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme

Davide Bertozzi

Shashi Kumar

Maurizio Palesi

Networks-on-Chip: Emerging Research Topics and Novel Ideas

One of the key steps in Network-on-Chip-based design is spatial mapping of cores 
	and routing of the communication between those cores. Known solutions to the mapping and 
	routing problems first map cores onto a topology and then route communication, using separate
	 and possibly conflicting objective functions. In this paper, we present a unified single-objective 
	 algorithm, called Unified MApping, Routing, and Slot allocation (UMARS+). As the main 
	 contribution, we show how to couple path selection, mapping of cores, and
channel time-slot allocation to minimize the network required to meet the constraints of 
the application. The time-complexity of UMARS+ is low and experimental results indicate 
a run-time only <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mn>20</mml:mn><mml:mi>&#x0025;</mml:mi></mml:mrow></mml:math> higher than that of path selection alone. We apply the algorithm to an MPEG 
 decoder System-on-Chip, reducing area by <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mn>33</mml:mn><mml:mi>&#x0025;</mml:mi></mml:mrow></mml:math>, power dissipation by <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mn>35</mml:mn><mml:mi>&#x0025;</mml:mi></mml:mrow></mml:math>, and worst-case latency by a factor four over a traditional waterfall approach.

Andreas  Hansson

Kees  Goossens

Andrei  R&#259;dulescu

A Unified Approach to Mapping and Routing on a  Network-on-Chip for Both Best-Effort and Guaranteed   Service Traffic

We propose link structures for NoC that have properties for tolerating efficiently transient, intermittent, and permanent errors. This is a necessary step to be taken in order to implement reliable systems in future nanoscale technologies. The protection against transient errors is realized using Hamming coding and interleaving for error detection and retransmission as the recovery method. We introduce two approaches for tackling the intermittent and permanent errors. In the first approach, spare wires are introduced together with reconfiguration circuitry. The other approach uses time redundancy, the transmission is split into two parts, where the data is doubled. In both structures the presence of permanent or intermittent errors is monitored by analyzing previous error syndromes. The links are based on self-timed signaling in which the handshake signals are protected using triple modular redundancy. We present the structures, operation, and designs for the different components
of the links. The fault tolerance properties are analyzed using a fault model containing temporary, intermittent, and permanent faults that occur both as bursts and as single faults. The results show a considerable enhancement in the fault tolerance at the cost of performance and area, and with only a slight increase in power consumption.

Teijo Lehtonen

Pasi Liljeberg

Juha Plosila

Online Reconfigurable Self-Timed Links for Fault Tolerant NoC

High-performance long-range NoC link enables efficient implementation of network-on-chip topologies which inherently require high-performance long-distance point-to-point communication such as torus and fat-tree structures. In addition, the performance of other topologies, such as mesh, can be improved by using high-performance link between few selected remote nodes. We presented novel implementation of high-performance long-range NoC link based on multilevel current-mode signaling and delay-insensitive two-phase 1-of-4 encoding. Current-mode signaling reduces the communication latency of long wires significantly compared to voltage-mode signaling, making it possible to achieve high throughput without pipelining and/or using repeaters. The performance of the proposed multilevel current-mode interconnect is analyzed and compared with two reference voltage mode interconnects. These two reference interconnects are designed using two-phase 1-of-4 encoded voltage-mode signaling, one with pipeline stages and the other using optimal repeater insertion. The proposed multilevel current-mode interconnect achieves higher throughput and lower latency than the two reference interconnects. Its throughput at 8 mm wire length is 1.222 GWord/s which is 1.58 and 1.89 times higher than the pipelined and optimal repeater insertion interconnects, respectively. Furthermore, its power consumption is less than the optimal repeater insertion voltage-mode interconnect, at 10 mm wire length its power consumption is 0.75 mW while the reference repeater insertion interconnect is 1.066 mW. The effect of crosstalk is analyzed using four-bit parallel data transfer with the best-case and worst-case switching patterns and a transmission line model which has both capacitive coupling and inductive coupling.

Ethiopia  Nigussie

Teijo  Lehtonen

Sampo  Tuuna

Juha  Plosila

Jouni  Isoaho

High-Performance Long NoC Link Using Delay-Insensitive Current-Mode Signaling

Networks-on-Chip (NoCs) are emerging as scalable interconnection architectures, designed to support the increasing amount of cores that are integrated onto a silicon die. Compared to traditional interconnects, however, NoCs still lack well established CAD deployment tools to tackle the large amount of available degrees of freedom, starting from the choice of a network topology. “Silicon-aware” optimization tools are now emerging in literature; they select an NoC topology taking into account the tradeoff between performance and hardware cost, that is, area and power consumption. A key requirement for the effectiveness of these tools, however, is the availability of accurate analytical models for power and area. Such models are unfortunately not as available and well understood as those for traditional communication fabrics. Further, simplistic models may turn out to be totally inaccurate when applied to wire dominated architectures; this observation demands at least for a model validation step against placed and routed devices. In this work, given an NoC reference architecture, we present a flow to devise analytical models of area occupation and power consumption of NoC switches, and propose strategies for coefficient characterization which have different tradeoffs in terms of accuracy and of modeling activity effort. The models are parameterized on several architectural, synthesis-related, and traffic variables, resulting in maximum flexibility. We finally assess the accuracy of the models, checking whether they can also be applied to placed and routed NoC blocks.

Paolo Meloni

Igor Loi

Federico Angiolini

Salvatore Carta

Massimo Barbaro

Luigi Raffo

Luca Benini

Area and Power Modeling for Networks-on-Chip with Layout Awareness

Networks on chip (NoCs) are an essential component
of systems on chip (SoCs) and much research is devoted
to deadlock avoidance in NoCs. Prior work focuses on the router
network while protocol interactions between NoC and intellectual
property (IP) modules are not considered. These interactions
introduce message dependencies that affect deadlock properties
of the SoC as a whole. Even when NoC and IP dependency
graphs are cycle-free in isolation, put together they may still
create cycles. Traditionally, SoCs rely solely on request-response protocols.
However, emerging SoCs adopt higher-level protocols for cache
coherency, slave locking, and peer-to-peer streaming, thereby
increasing the complexity in the interaction between the NoC
and the IPs. In this paper, we analyze message-dependent deadlock, arising
due to protocol interactions between the NoC and the IP
modules. We compare the possible solutions and show that
deadlock avoidance, in the presence of higher-level protocols,
poses a serious challenge for many current NoC architectures.
We evaluate the solutions qualitatively, and for a number of
designs we quantify the area cost for the two most economical
solutions, strict ordering and end-to-end flow control. We show
that the latter, which avoids deadlock for all protocols, adds an
area and power cost of 4<mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>&#x0025;</mml:mi></mml:math> and 6<mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>&#x0025;</mml:mi></mml:math>, respectively, of a typical &#198;thereal NoC instance.

Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip

Network-on-chip- (NoC-) based application-specific systems on chip, where information traffic is heterogeneous and delay requirements may largely vary, require individual capacity assignment for each link in the NoC. This is in contrast to the standard approach of on- and off-chip interconnection networks which employ uniform-capacity links. Therefore, the allocation of link capacities is an essential step in the automated design process of NoC-based systems. The algorithm should minimize the communication resource costs under Quality-of-Service timing constraints. This paper presents a novel analytical delay model for virtual channeled wormhole networks with nonuniform links and applies the analysis in devising an efficient capacity allocation algorithm which assigns link capacities such that packet delay requirements for each flow are satisfied.

Zvika Guz

Isask'har Walter

Evgeny Bolotin

Israel Cidon

Ran Ginosar

Avinoam Kolodny

Network Delays and Link Capacities in Application-Specific Wormhole NoCs

As CMOS technology scales down into the deep-submicron (DSM) domain, the costs of design
and verification for Systems-on-Chip (SoCs) are rapidly increasing. Relaxing the requirement of <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mn>100</mml:mn><mml:mi>&#x0025;</mml:mi></mml:mrow></mml:math> correctness
for devices and interconnects drastically reduces the costs of design but, at the same time, requires
SoCs to be designed with some degree of system-level fault-tolerance. Towards this end, this paper introduces a
novel communication paradigm for SoCs, called stochastic communication. This scheme separates communication
from computation by allowing the on-chip interconnect to be designed as a reusable IP and also provides a
built-in tolerance to DSM failures, without a significant performance penalty. By using this communication
scheme, a large percentage of data upsets, packet losses due to buffers overflow, and severe levels of synchronization
failures can be tolerated, while providing high levels of performance.

Paul  Bogdan

Tudor  Dumitra&#351;

Radu  Marculescu

Stochastic Communication: A New Paradigm for Fault-Tolerant Networks-on-Chip

Networks on Chips (NoCs) are required to tackle the increasing delay and poor scalability issues of bus-based communication architectures. Many of today's NoC designs are based on single path routing. By utilizing multiple paths for routing, congestion in the network is reduced significantly, which translates to improved network performance or reduced network bandwidth requirements and power consumption. Multiple paths can also be utilized to achieve spatial redundancy, which helps in achieving tolerance against faults or errors in the NoC. A major problem with multipath routing is that packets can reach the destination in an out-of-order fashion, while many applications require in-order packet delivery. In this work, we present a multipath routing strategy that guarantees in-order packet delivery for NoCs. It is based on the idea of routing packets on partially nonintersecting paths and rebuilding packet order at path reconvergent nodes. We present a design methodology that uses the routing strategy to optimally spread the traffic in the NoC to minimize the network bandwidth needs and power consumption. We also integrate support for tolerance against transient and permanent failures in the NoC links in the methodology by utilizing spatial and temporal redundancy for transporting packets. Our experimental studies show large reduction in network bandwidth requirements (36.86<mml:math id="E1" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>%</mml:mi></mml:math> on average) and power consumption (30.51<mml:math id="E2" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>%</mml:mi></mml:math> on average) compared to single-path systems. The area overhead of the proposed scheme is small (a modest 5<mml:math id="E3" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>%</mml:mi></mml:math> increase in network area). Hence, it is practical to be used in the on-chip domain.

Srinivasan Murali

David Atienza

Giovanni De Micheli

A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Gaurantees

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Networks-on-Chip

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VLSI Design

Networks-on-Chip

Networks-on-Chip

Articles

Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme

Networks-on-Chip: Emerging Research Topics and Novel Ideas

A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic

Online Reconfigurable Self-Timed Links for Fault Tolerant NoC

High-Performance Long NoC Link Using Delay-Insensitive Current-Mode Signaling

Area and Power Modeling for Networks-on-Chip with Layout Awareness

Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip

Network Delays and Link Capacities in Application-Specific Wormhole NoCs

Stochastic Communication: A New Paradigm for Fault-Tolerant Networks-on-Chip

A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Gaurantees