- About this Journal ·
- Abstracting and Indexing ·
- Aims and Scope ·
- Article Processing Charges ·
- Articles in Press ·
- Author Guidelines ·
- Bibliographic Information ·
- Citations to this Journal ·
- Contact Information ·
- Editorial Board ·
- Editorial Workflow ·
- Free eTOC Alerts ·
- Publication Ethics ·
- Reviewers Acknowledgment ·
- Submit a Manuscript ·
- Subscription Information ·
- Table of Contents
International Journal of Microwave Science and Technology
Volume 2013 (2013), Article ID 584341, 11 pages
An Inductorless Cascaded Phase-Locked Loop with Pulse Injection Locking Technique in 90 nm CMOS
Solutions Research Laboratory, Tokyo Institute of Technology, 4259-S2-14 Nagatsuta, Midori-ku, Yokohama 226-8503, Japan
Received 1 December 2012; Accepted 21 January 2013
Academic Editor: Leonid Belostotski
Copyright © 2013 Sang-yeop Lee et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
An inductorless phase-locked loop with subharmonic pulse injection locking was realized (PLL area: 0.11 mm2) by adopting 90 nm Si CMOS technology. The proposed circuit is configured with two cascaded PLLs; one of them is a reference PLL that generates reference signals to the other one from low-frequency external reference signals. The other is a main PLL that generates high-frequency output signals. A high-frequency half-integral subharmonic locking technique was used to decrease the phase noise characteristics. For a 50 MHz input reference signal, without injection locking, the 1 MHz offset phase noise was −88 dBc/Hz at a PLL output frequency of 7.2 GHz (= 144 × 50 MHz); with injection locking, the noise was −101 dBc/Hz (spur level: −31 dBc; power consumption from a 1.0 V power supply: 25 mW).
Conventional multistandard wireless mobile terminals contain multiple RFICs. To reduce production costs, one-chip wideband RF LSI systems are desired. A great effort is being made to develop wideband and/or multiband RF solutions using highly scaled advanced CMOS processes. The use of such processes is beneficial to and converters and digital baseband circuits. However, it is very difficult to reduce the scale of RF/analog circuit blocks, especially power amplifiers and oscillator circuits, including voltage-controlled oscillators (VCOs) and phase-locked loops (PLLs), because of the presence of inductors that do not scale with advancements in technology.
In designing VCOs which generate signals in RF systems, ring-type VCOs (ring VCOs) are more attractive than LC-resonant-type VCOs (LC VCOs) in terms of their small area and wide frequency tuning range since they do not use large passive devices. However, they have poor phase noise with relatively high power consumption. Nevertheless, low-phase-noise ring VCO is still a possibility if some noise-suppression mechanism is applied. One of available options would be injection locking.
In the early days, Adler  and many other authors studied the behavior of VCOs with injection locking. Also, there are numerous papers published in reference to VCOs with injection locking in order to achieve phase locking and high performances. Moreover, recently, PLLs with an injection-locked frequency divider and frequency multiplier, and a clock and data recovery circuit (CDR) were presented.
This paper describes a study on a ring-VCO-based PLL with pulse injection locking as a potential solution to realize a scalable inductorless PLL, which can generate wideband frequency signal with low supply voltage. Usually, the frequency range utilized consumer RF applications, such as wireless LAN a/b/g/n, Bluetooth, and digital TV (DTV), is very wide and spreading from 400 MHz to 6 GHz. Table 1 shows target performance of the proposed PLL. Generally, in RF systems using high transmitting power, a frequency synthesizer should generate higher-frequency signals up to 12 GHz to avoid injection pulling from a power amplifier. Then, some methods, such as using frequency dividers and mixers, are applied to widen frequency range [2, 3].
In addition, the proposed PLL is augmented with high-frequency half-integral subharmonic locking in order to improve its phase-noise performance. In Section 2, brief features of the proposed PLL are explained. In Section 2.1, high-frequency half-integral subharmonic locking is shown as a method of reducing phase noise. Also, the proposed cascaded PLL (CPLL) that can achieve injection locking at high frequencies from low-frequency reference is presented. Detailed circuit designs, such as a VCO and a charge pump which are able to realize wide-band operation, and the measurement results obtained from an implementation in 90 nm CMOS process are presented in Sections 3 and 4, respectively. Finally, we conclude this work in Section 5.
2. Injection Locking in Frequency Synthesizers
Figure 1 shows an injection-locked PLL (ILPLL). The PLL is based on a ring VCO that is able to generate high-frequency outputs across wide frequency range, as well as outputs. The PLL also consists of a phase frequency detector (PFD), a charge pump (CP), a loop filter (LF), a variable delay unit (), and a pulser.
PLLs that use ring type VCOs are required to have a wide loop bandwidth of the phase-locked loop for lowering their poor phase noise characteristics. However, there is a trade-off between the loop bandwidth and the stability of PLLs. In general, the loop bandwidth () must be narrower than ~, where is the reference-signal frequency . Consequently, there is a limitation on lowering the phase noise in ring-VCO-based charge-pump PLLs (CP PLLs). Figure 2 shows phase noise characteristics of the PLL. In this case, the charge-pump noise of the PLL is assumed to be small enough and can be neglected. In Figure 2, phase noise is suppressed up to the loop bandwidth () by the noise filtering of the loop. On the other hand, pulse injection locking is effective to reduce phase noise of ring VCOs since ring VCOs have a wider lock range with injection locking than that of LC VCOs because of their low quality factors. In designing subharmonically injection-locked oscillators (ILOs), times frequency-multiplied signals as to the reference frequency can be achieved. The lock range is decided by the power of th superharmonics of the reference signal as follows [1, 5]: where represents the open-loop quality factor of an oscillator (calculated by using the open-loop transfer function of the oscillator ), is the output frequency of the oscillator under injection locked condition, is the th harmonic power of the reference signal, and is the free-running output power of the oscillator. is approximately given by where is the pulse amplitude, is the duty cycle of pulses (, : pulse width, : period of pulses). From (1) and (2), the lock range can be rewritten as follows: where () is the injection-signal frequency .
The overall ILO output phase noise is obtained by adding the noise contributions in an ILO. Assuming that , , and are phase noise power functions of an injection-locked VCO, a reference signal, and a free-running VCO, respectively, the phase noise of an ILO, , simply can be expressed as where is the normalized phase noise power function with respect to the output frequency of , and means the ratio between the output frequency () and the input frequency (). and are low-pass and high-pass transfer functions, respectively . Supposed that and have the first-order transfer functions and they have the same cutoff frequency of , the simple equation of (4) would be achieved [5, 9, 10].
In the proposed PLL, there are two kinds of phase locking mechanism: one is a phase-locked loop, and the other is pulse injection locking. In general, either of them is enough for phase locking. However, those two mechanisms are combined to get a wide frequency range operation with a low-phase-noise performance. The phase-locked loop, which uses a charge pump for controlling the oscillation frequency, is implemented to ensure correct frequency locking over the entire VCO tuning range. The final phase locking is done by injection locking to reference signal [11–13].
2.1. High-Frequency Half-Integral Subharmonic Locking Topology for Noise Reduction
A paper on half-integral subharmonic injection locking based on the use of a ring VCO has been presented . A differential VCO can be easily designed to lock to half-integral subharmonics by giving its necessary symmetry properties. Suppose that a VCO consists of differential circuits and has a certain symmetry. As a method to achieve injection locking, a direct injection technique is applied, which uses nMOS switches that short the differential outputs for phase corrections. Figure 3 shows differential waveforms (, ) of the VCO in the case of both integral () and half-integral subharmonic locking (). The two output nodes are shorted when the injection signal (, ) is input into the nMOS switches. Phase corrections may occur at the time and the jitter is reduced. Generally, there are two points of time during the period of the output signal when two output nodes can be shorted because of topological symmetry as shown in Figure 3. Consequently, the differential VCO is capable of both integral and also half-integral subharmonic locking.
One advantage of using half-integral subharmonic locking is to be able to use high-frequency reference signal and can make the locking range of injection locking, wide as shown in (1). Figure 2 and Equation (4) also show that the phase noise of the reference signal mainly affects the output phase noise at low offset frequencies and that the phase noise of the PLL becomes dominant as the offset frequency approaches the edge of the locking range . Therefore, it will improve phase noise characteristics to the edge of the locking range to use high-frequency reference signals.
2.2. High-Frequency Signal Generation with Cascaded ILOs
As shown in (3), the lock range is proportional to the input frequency of . However, narrower pulses are required to achieve smaller with increasing the multiplication ratio (). Unfortunately, it is difficult to achieve sufficiently narrow pulses even with the use of nm-scale CMOS processes since the reference inputs also have certain jitter and parasitic components of the pulser limit the pulse width. In other words, there is limitation to generate high-frequency (over 5 GHz) injection-locked signals with low-frequency reference such as XTALs.
One solution is to employ cascaded oscillators , which make each multiplication ratio () smaller by using two multiplication processes. Figure 4 shows the concept of the cascaded ILOs. Firstly, the input signal, which has sufficiently high-power superharmonics, is injected into VCO1. Then, multiplied frequency signal () of the reference frequency can be achieved by tuning the VCO1 oscillation frequency properly. In this case, the output phase noise of VCO1 with injection locking can be expressed as follows: where is the lock range that is proportional to the input frequency () and can be calculated from (3).
The output signal of VCO1 is injected into VCO2 and locked to the output of VCO2 with the same process occurred in VCO1. Also, the output phase noise of VCO2 with injection locking can be expressed as follows: where is the ratio between the output frequency of VCO2 () and input frequency () and is the lock range of VCO2. When the offset frequency of is sufficiently lower than (i.e., ), (7) is held. In other words, sufficiently wide lock range makes it possible to neglect the secondary VCO phase noise up to the lock range in cascaded ILOs.
3. Proposed Injection-Locked PLL Topology
Figure 5 shows the configuration of the proposed PLL that enables the use of half-integral subharmonic locking, which was proposed in our previous work . The proposed PLL consists of two injection-locked PLLs. A reference PLL, namely, RPLL generates reference signals to a main PLL, namely, MPLL from low-frequency external reference signals. In this topology, when we choose divider ratios (Table 2), respectively as, , , and , the ratio between the reference signal to MPLL and the output frequency of MPLL may be 4.5 and high-frequency half-integral subharmonic locking can be applied. Variable time delay cells s are implemented to control the time when injection signals are input because phase corrections can occur easily when differential output nodes are shorted in the direct injection locking scheme (Figure 3).
3.1. Main PLL
Figure 6(a) shows the topology of the proposed delay cell that composes a ring VCO . The delay cell contains an inverter latch as a negative conductance circuit that generates delay by positive feedback in order to satisfy the oscillation condition . To tune the VCO output frequency widely, variable pMOS resistive loads are used. However, in the commonly used delay cells with pMOS resistive loads, the range of control voltage is limited from 0 V to the pMOS threshold voltage. In the proposed delay cell, a pMOS transistor is added into which the subcontrol voltage () is input in order to make the range of sensitive voltages identical to the rail-to-rail voltage range (0 V to ). For this purpose, the bias level shifted by about , , is input to the added pMOS transistor. As a result, the total equivalent resistance of the two pMOS transistors in parallel changes almost linearly versus the main control voltage, . Consequently, the VCO output frequency can be tuned linearly across the wide tuning range [12, 13]. An nMOS switches are connected at the nodes between the differential nodes to achieve injection locking .
The proposed ring VCO is shown in Figure 6(b). It is based on a two-stage pseudo differential ring oscillator. Pulses which are generated by the on-chip pulser are injected into the left delay cell in the form of rail-to-rail pulses for injection locking. To maintain topological symmetry, an nMOS switch biased to 0 V is also applied in the right-side delay cell. We achieved the VCO tuning range of 6.02 GHz to 11.1 GHz across the rail-to-rail control voltage from the postlayout simulation of the VCO core with output buffers (90 nm CMOS process, ).
A tristate phase/frequency detector (PFD) is implemented, which consists of two D-flip flops, delay-path inverters, and an AND logic. The PFD detects phase and frequency difference between the reference signal and the divided VCO output and generates output pulses of and which are input into the charge pump to reduce the difference.
Figure 7 shows an implemented current mirror circuit to generate stable constant current from the charge pump. Usually, stacked current mirrors design can obtain better DC headroom and linearity with longer channel lengths as shown in the left side of Figure 7. In this case, DC headroom of the output voltage () is expressed as , where is the overdrive voltage of MOS transistors (M3, M4), and is an nMOS threshold voltage. In the case of Sooch cascode current mirror as shown in the right side of Figure 7, the MOS transistor, M5, is forced to operate in the triode region. The DC headroom can be reduced as since MOS transistors operate in the saturation region except for M5 . Consequently, low voltage operation can be achieved.
Proposed current switching charge pump (CP) that employs Sooch cascode current mirror is shown in Figure 8. Dummy switches are also implemented to maintain the balance between PFD outputs. Two external current sources ranged from μA to μA are used.
Figure 9 shows postlayout simulation results of the proposed charge pump, when μA (90 nm CMOS process, 1.0 V supply). It shows that the charge pump can generate quite constant output current across the wide range of the output voltage (). When V and V, the result shows current mismatch between the up and down output currents as a function of the output voltage (). The percentage mismatch error for 0.48 is less than 2% and increases to less than 5% for 0.21 .
A second-order lag-lead filter that consists of a register and two capacitors is implemented as a loop filter (LF) of the loop to suppress the charge-pump ripple. ( kΩ, pF, pF). In this case, on-chip MIM capacitors were used.
The frequency divider consists of differential pseudo-nMOS latches to minimize chip area and achieve low power consumption . The frequency divider chain consists of three divide-by-2 circuits and one divide-by-2/3 circuit. As a result, it can divide by 24 and 36 in the loop (i.e., divider ratio ).
The loop dynamic characteristics are designed to have the unity-gain bandwidth of 2.8 MHz and phase margin of 16° (VCO gain: 5 GHz/V, μA, divider ratio ). When the divider ratio equals to 36, the unity-gain bandwidth of 2.2 MHz and phase margin of 19° are achieved. The PLL has poor phase margin that is related to the low damping factor and the slow settling time, because final phase locking is done not only by the phase-locked loop but also by injection locking. Injection locking that is applied into a phase-locked loop helps the phase margin to be improved . In this case, large capacitance of is required to suppress the reference spur level due to the control voltage ripple. A loop bandwidth of the PLL is designed to be small enough compared to the lock range of injection locking to avoid the interference between two phase locking but can still achieve frequency locking.
To achieve subharmonic locking, an AND-based pulser is used, which is able to tune the pulse width below 40 ps by the analog control. Also, a variable time-delay unit () which consists of inverters and tristate inverters was applied to match the zero-crossing points of differential VCO outputs to the pulses for effective injection locking.
3.2. Reference PLL
The proposed ring VCO used in RPLL is based on a four-stage pseudo differential ring oscillator. The same delay cell shown in MPLL (Figure 6(a)) is applied to widen frequency tuning range linearly. Also, long-gate channel MOS transistors are equipped in the delay cell to decrease VCO oscillation frequencies and reduce flicker noise characteristics as a reference signal into MPLL. Pulses which are generated by the on-chip pulser are injected into the left delay cell in the form of rail-to-rail pulses for injection locking. To maintain topological symmetry, an nMOS switch biased to 0 V is also applied in the other delay cells. We achieved the VCO tuning range of 0.805 GHz to 2.85 GHz across the rail-to-rail control voltage from the postlayout simulation of the VCO core with output buffers (90 nm CMOS process, ).
The tristate PFD and CP presented in Figure 8 are implemented in RPLL. With postlayout simulation results of the charge pump (90 nm CMOS process, 1.0 V supply), the percentage mismatch error () for 0.32 is less than 2% and increases to less than 5% for 0.24 ( V, V).
As a loop filter (LF), a second-order lag-lead filter is implemented. The filter consists of a register ( kΩ), and two on-chip capacitors ( pF, pF). The frequency divider chain in RPLL consists of five divide-by-2 circuits. As a result, it can divide by 32 (i.e., divider ratio ). Finally, the AND-based pulser and the variable time-delay unit () were implemented for effective injection locking. In RPLL, an injection frequency of is same to a reference frequency of .
4. Measurement Results
4.1. Main PLL (MPLL)
Figures 10(a) and 10(b) show chip micrograph of the differential ring VCO and a PLL, respectively. To clear the effectiveness of the proposed PLL, the VCO cell used in the PLL was also fabricated. They were fabricated by a 90 nm Si CMOS process. The area of the ring VCO core is 0.030 × 0.045 mm2 including the bias-level-shift circuit and the pulser. The PLL circuit occupies an area of 0.38 × 0.21 mm2. They were measured in 1.0 V supply condition. Also, the PLL circuit was measured using 20 μA-current-sources () into the charge pump.
During free-running operation, the frequency tuning range of the VCO was from 6.35 GHz to 11.5 GHz as shown in Figure 11. It was measured by using an Agilent Technologies E5052B signal source analyzer. It also shows that the VCO output frequency could be tuned quite linearly versus the rail-to-rail control voltage () due to the bias-level-shift circuit. When the VCO output frequency () is 7.18 GHz, the total power consumption of the VCO (with the bias-level-shift circuit and pulser) was 8.4 mW.
Phase noise characteristics of the VCO and PLL at GHz without and with injection locking are shown in Figure 12 as measured by the signal source analyzer. In addition to them, phase noise characteristics of the 300 MHz reference signal are shown in Figures 12 and 14. A 1 MHz-offset phase noise of dBc/Hz was generated in the free-running VCO. With injection locking, a 1 MHz offset phase noise of dBc/Hz was generated, which was improved by 32 dB compared to the former. On the other hand, a 1 MHz-offset phase noise of dBc/Hz was generated in the PLL when the PLL was only locked by the phase-locked loop. Due to the poor phase margin, gain peaking at the offset frequency of about 3 MHz was observed. With injection locking, a 1 MHz offset phase noise of dBc/Hz was generated, which was improved by 16 dB compared to the former.
Figure 13 shows calculated phase noise characteristics by using (4) and the measurement phase noise of the free-running VCO and the reference signal as shown in Figure 12. The results show that wider lock range makes lower phase noise characteristics within the lock range. From the calculated result of MHz, (4) is well matched to the measurement results except the offset-frequency region up to about 30 kHz. It is because that flicker noise model as expressed in  is not included for simplicity and certain spurs occurred at the offset frequency of about 10 KHz were measured.
Phase noise characteristics of the VCO and PLL at GHz are shown in Figure 14. A 1MHzoffset phase noise of dBc/Hz and dBc/Hz were generated in the free-running VCO and the PLL, respectively. Phase noise reduction with injection locking could not be achieved since it was difficult to generate effective injection pulses with sufficient power for achieving the injection-locked condition at that high output frequency.
4.2. Cascaded PLL
Figure 15 shows a chip micrograph of the proposed CPLL. It was fabricated by a 90 nm Si CMOS process. It includes both RPLL and MPLL that occupy an area of mm2. It was measured in 1.0 V supply condition. Also, the PLL circuit was measured using μA current sources into RPLL charge pump and μA current-sources into MPLL charge pump. RPLL was locked to reference signals of 50 MHz which were generated by the pulse pattern generator.
Figure 16 shows the phase noise characteristics at GHz (= 32 × 50 MHz) as measured by an Agilent Technologies E5052A signal source analyzer. Without injection locking, a 1 MHz-offset phase noise of dBc/Hz was generated in RPLL. Due to the poor phase margin, gain peaking at the offset frequency of about 4 MHz was observed. With injection locking, the measured phase noise was dBc/Hz at an offset of 1 MHz. It shows a 16 dB phase-noise reduction with injection locking. Also, phase noise characteristics of the external reference signal are shown Figure 16. At 10 KHz and 1 MHz offset, the phase noise of the reference signal were and dBc/Hz, respectively.
Figure 17 shows the phase noise characteristics at GHz (= 144 × 50 MHz). 0.2 GHz injection signals were injected when , , and are corresponding to 36, 8, and 8, respectively. Also, 1.6 GHz injection signals were injected when , , and are corresponding to 36, 1, and 8, respectively. Without injection into MPLL, a 1 MHz offset phase noise of dBc/Hz was generated in the PLL. With integral subharmonic injection locking (, GHz), the measured phase noise was dBc/Hz at an offset of 1 MHz. With high-frequency half-integral subharmonic locking (, GHz), we successfully achieved 2 dB lower phase noise at 1 MHz offset than the former. A 4 MHz offset phase noise was improved by 4 dB in the latter case, compared with the former. The results show that high-frequency reference injections can widen the injection lock range. However, there was a spur around the offset frequency of 25 MHz owing to the RPLL spur level, and the spur limited the lock range widening with high-frequency signal injections.
Usually, spurs are induced by periodic phase shift due to injection locking. The spur level can be expressed as follows: where represents the spur levels occurred by the reference signal at , and is the injection-locked output power of the oscillator . As shown in this equation, the spur level would be reduced lowering the lock range with the same reference frequency, however, which is undesirable to reduce phase noise characteristics.
Calculated phase noise characteristics by using (6) and measure phase noise characteristics, as shown in Figures 12 and 16, are shown in Figure 18. In this case, the lock range was supposed to be proportional to the input frequency and the coefficient was 0.14, which was expected in Figure 13. In the results, phase noise characteristics especially at the offset frequency of 500 kHz, 700 kHz, and lower than 5 kHz due to the secondary VCO (VCO2) would be reduced by using high-frequency injection signals ( GHz, MHz). In Figure 18, measured phase noise characteristics from the offset frequency of 30 kHz to 1 MHz were degraded compared with calculated results due to induced noise from the MPLL loop.
Figure 19 shows the phase noise characteristics at GHz (= 192 × 50 MHz). In these cases, , , and are corresponding to 24, 8, and 8, respectively. Without injection into MPLL, a 1 MHz offset phase noise of dBc/Hz was generated in the PLL. With integral subharmonic injection locking (, GHz), the measured phase noise was dBc/Hz at an offset of 1 MHz. In Figure 19, spur levels around the offset frequency of 25 MHz were decreased, because the phase-locking effect of injection locking was decreased.
The PLL generated reference spurs of lower than dBc at the output frequency of 7.2 GHz with 1.6 GHz injections, as shown in Figure 20(a). At the output frequency of 9.6 GHz with 0.2 GHz injections, reference spurs of lower than dBc were measured as shown in Figure 20(b).
A performance summary at the output frequency of 7.2 GHz of the fabricated chips are given in Table 3, when injection locking was established. It shows that high-frequency injections are effective to reduce the phase noise because a wide injection lock range can be achieved.
A performance comparison of the PLL with other PLLs that were designed using various kinds of phase-locking methods is given in Table 4. Unfortunately, the proposed PLL cannot cover wide frequency range from 6 GHz to 12 GHz as shown in Table 1, due to the VCO tuning range and limitation of tunable divider ratio. To make a fair in-band phase noise comparison between various kinds of PLL designs, the dependency of in-band phase noise on and should be normalized out . Therefore, normalized in-band phase noise was applied for comparison. The proposed PLL shows a relatively good value. Also its area and power consumption are small and comparable to that of other circuits.
An inductorless PLL architecture, using the combination of a phase-locked loop, and injection locking with a ring VCO was proposed. The proposed CPLL that consists of two PLLs was designed in order to generate high-frequency output signals with low-frequency external reference signals. High-frequency half-integral subharmonic injection locking to improve the phase noise characteristics of the inductorless PLL was implemented.
The injection-locked PLL was fabricated by adopting 90 nm Si CMOS technology. A 1 MHz-offset phase noise of dBc/Hz was achieved at an output frequency of 7.2 GHz, which was improved by 25 dB compared with that of the free-running VCO. The area of this inductorless PLL was as small as mm2 with low power consumption of 25 mW.
This work was partly supported by STARC, KAKENHI, MIC.SCOPE, and VDEC in collaboration with Agilent Technologies Japan, Ltd., Cadence Design Systems, Inc., and Mentor Graphics, Inc. The authors also acknowledge the JSPS Research Fellowship for Young Scientists from the Japan Society for the Promotion of Sciences.
- R. Adler, “A study of locking phenomena in oscillators,” Proceedings of the IRE, vol. 34, pp. 351–357, 1946.
- Y. Ito, H. Sugawara, K. Okada, and K. Masu, “A 0.98 to 6.6 GHz tunable wideband VCO in a 180 nm CMOS technology for reconfigurable radio transceiver,” in Proceedings of the IEEE Asian Solid-State Circuits Conference (ASSCC '06), pp. 359–362, November 2006.
- B. Razavi, “Cognitive radio design challenges and techniques,” The IEEE Journal of Solid-State Circuits, vol. 45, no. 8, pp. 1542–1553, 2010.
- F. M. Gardner, “Charge-pump phase-lock loops,” IEEE Transactions on Communications, vol. 28, no. 11, pp. 1849–1858, 1980.
- X. Zhang, X. Zhou, and A. S. Daryoush, “A theoretical and experimental study of the noise behavior of subharmonically injection locked local oscillators,” IEEE Transactions on Microwave Theory and Techniques, vol. 40, no. 5, pp. 895–902, 1992.
- B. Razavi, “A study of phase noise in CMOS oscillators,” IEEE Journal of Solid-State Circuits, vol. 31, no. 3, pp. 331–343, 1996.
- S. Lee, N. Kanemaru, S. Ikeda et al., “A ring-VCO-based injection-locked frequency multiplier with novel pulse generation technique in 65 nm CMOS,” IEICE Transactions on Electronics, vol. 95, no. 10, pp. 1589–1597, 2012.
- Y. Kobayashi, S. Amakawa, N. Ishihara, and K. Masu, “A low-phase-noise injection-locked differential ring-VCO with half-integral subharmonic locking in 0.18 μm CMOS,” in Proceedings of the 35th European Solid-State Circuits Conference (ESSCIRC '09), pp. 440–443, September 2009.
- T. Sugiura and S. Sugimoto, “FM noise reduction of Gunn-effect oscillators by injection locking,” Proceedings of the IEEE, vol. 57, no. 1, pp. 77–78, 1969.
- M. C. Chen and C. Y. Wu, “Design and analysis of CMOS subharmonic injection-locked frequency triplers,” IEEE Transactions on Microwave Theory and Techniques, vol. 56, no. 8, pp. 1869–1878, 2008.
- J. Lee and H. Wang, “Study of subharmonically injection-locked PLLs,” The IEEE Journal of Solid-State Circuits, vol. 44, no. 5, pp. 1539–1553, 2009.
- S. Y. Lee, S. Amakawa, N. Ishihara, and K. Masu, “Low-phase-noise wide-frequency-range ring-VCO-based scalable PLL with subharmonic injection locking in 0.18 μm CMOS,” in Proceedings of the IEEE MTT-S International Microwave Symposium Digest (MTT '10), pp. 1178–1181, May 2010.
- S. Y. Lee, S. Amakawa, N. Ishihara, and K. Masu, “High-frequency half-integral subharmonic locked ring-VCO-based scalable PLL in 90 nm CMOS,” in Proceedings of the IEEE Asia-Pacific Microwave Conference (APMC '10), pp. 586–589, December 2010.
- B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, New York, NY, USA, 2001.
- M. Tiebout, “A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider,” IEEE Journal of Solid-State Circuits, vol. 39, no. 7, pp. 1170–1174, 2004.
- P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, John Wiley & Sons, New York, NY, USA, 4th edition, 2001.
- T. Sekiguchi, S. Amakawa, N. Ishihara, and K. Masu, “Inductorless 8.9 mW 25 Gb/s 1:4 DEMUX and 4 mW 13 Gb/s 4:1 MUX in 90 nm CMOS,” Journal of Semiconductor Technology and Science, vol. 10, no. 3, pp. 176–184, 2010.
- H. Kodama, H. Okada, H. Ishikawa, and A. Tanaka, “Wide lock-range, low phase-noise PLL using interpolative ring-VCO with coarse frequency tuning and frequency linearization,” in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC '07), pp. 349–352, September 2007.
- G. Y. Tak, S. B. Hyun, T. Y. Kang, B. G. Choi, and S. S. Park, “A 6.3–9 GHz CMOS fast settling PLL for MB-OFDM UWB applications,” IEEE Journal of Solid-State Circuits, vol. 40, no. 8, pp. 1671–1679, 2005.
- T. Y. Lu and W. Z. Chen, “A 3-to-10GHz 14-band CMOS frequency synthesizer with spurs reduction for MB-OFDM UWB system,” in Proceedings of the IEEE International Solid-State Circuits Conference—Digest of Technical Papers (ISSCC '08), pp. 126–601, February 2008.
- S. Ye, L. Jansson, and I. Galton, “A multiple-crystal interface PLL with VCO realignment to reduce phase noise,” IEEE Journal of Solid-State Circuits, vol. 37, no. 12, pp. 1795–1803, 2002.
- M. M. Izad and C. Heng, “A pulse shaping technique for spur suppression in injection-locked synthesizers,” The IEEE Journal of Solid-State Circuits, vol. 47, no. 3, pp. 652–664, 2012.
- X. Gao, E. A. M. Klumperink, M. Bohsali, and B. Nauta, “A 2.2 GHz 7.6 mW sub-sampling PLL with −126 dBc/Hz in-band phase noise and 0.15 psrms jitter in 0.18 μm CMOS,” in Proceedings of the IEEE International Solid-State Circuits Conference—Digest of Technical Papers (ISSCC '09), pp. 392–393, 393a, February 2009.