We propose a novel circuit technique to generate a reduced voltage swing (RVS) signals for active power reduction on main buses and clocks. This is achieved without performance degradation, without extra power supply requirement, and with minimum area overhead. The technique stops the discharge path on the net that is swinging low at a certain voltage value. It reduces active power on the target net by as much as 33&#37; compared to traditional full swing signaling. The logic 0 voltage value is programmable through control bits. If desired, the reduced-swing mode can also be disabled. The approach assumes that the logic 0 voltage value is always less than the threshold voltage of the nMOS receivers, which eliminate the need of the low to high voltage translation. The reduced noise margin and the increased leakage on the receiver transistors using this approach have been addressed through the selective usage of multithreshold voltage (MTV) devices and the programmability of the low voltage value.

Khader Mohammad

Ayman Dodin

Bao Liu

Sos Agaian

Reduced Voltage Scaling in Clock Distribution Networks

Cost-effective Networks-on-Chip (NoCs) routers are important for future SoCs and embedded devices. Implementation results show that the generic virtual channel allocator (VA) and the generic switch allocator (SA) of a router consume large amount of area and power. In this paper, after a careful study of the working principle of a VA and the utilization statistics of its arbiters, opportunities to simplify the generic VA are identified. Then, the deadlock problem for a combined switch and virtual channel allocator (SVA) is studied. Next, the impact of the VA simplification on the router critical paths is analyzed. Finally, the generic architecture and two low-cost architectures proposed (the look-ahead, and the SVA) are evaluated with a cycle-accurate network simulator and detailed VLSI implementations. Results show that both the look-ahead and the SVA significantly reduce area and power compared to the generic architecture. Furthermore, cost savings are achieved without performance penalty.

Min Zhang

Chiu-Sing Choy

Low-Cost Allocator Implementations for Networks-on-Chip Routers

This paper focuses on leakage reduction at architecture and arithmetic level. A methodology for considerable reduction of the static power consumption is shown. Simulations are done in a typical 130&#x2009;nm CMOS technology. Based on the simulation results, the static power consumption is estimated and compared for different filter architectures. Substantial power reductions are shown in both FIR-filters and IIR-filters. Three different types of architectures, namely, bit-parallel, digit-serial, and bit-serial structures are used to demonstrate the methodology. The paper also shows that the relative power ratio is strongly dependent on the used word length; that is, the gain in power ratio is larger for longer word lengths. A static power ratio at 0.48 is shown for the bit-serial FIR-filter and a power ratio at 0.11 is shown in the arithmetic part of the FIR-filter. The static power ratio in the IIR-filter is 0.36 in the bit-serial filter and 0.06 in the arithmetic part of the filter. It is also shown that the use of storage, such as registers, relatively the arithmetic part, affects the power ratio. The relatively lower power consumption in the IIR-filter compared to the FIR-filter is due to the lower use of registers.

Peter Nilsson

Architectures and Arithmetic for Low Static Power Consumption in Nanoscale CMOS

Routing in nanometer 
                  nodes creates an elevated level of importance 
                  for low-congestion routing. At the same time, 
                  advances in mathematical programming have 
                  increased the power to solve complex problems, 
                  such as the routing problem. Hence, new routing 
                  methods need to be developed that can 
combine advanced mathematical programming and modeling techniques 
to provide low-congestion solutions. In this paper, a hierarchical 
mathematical programming-based global routing technique that 
considers congestion is proposed. The main contributions presented 
in this paper include (i) implementation of congestion estimation 
based on actual routing solutions versus purely probabilistic 
techniques, (ii) development of a congestion-based hierarchy for 
solving the global routing problem, and (iii) generation of a 
robust framework for solving the routing problem using 
mathematical programming techniques. Experimental results 
illustrate that the proposed global router is capable of reducing 
congestion and overflow by as much as 36% compared to the 
state-of-the-art mathematical programming models.

Logan Rakai

Laleh Behjat

Shawki Areibi

Tamas Terlaky

A Multilevel Congestion-Based Global Router

As the semiconductor technology advances, interconnect plays a more and more important role in power consumption in VLSI systems. This also imposes a challenge in high-level synthesis, in which physical information is limited and conventionally considered after high-level synthesis. To close the gap between high-level synthesis and physical implementation, integration of physical synthesis and high-level synthesis is essential. In this paper, a technique named FloM is proposed for integrating floorplanning into high-level synthesis of VLSI system with multivoltage datapath. Experimental results obtained show that the proposed technique is effective and the energy consumed by both the datapath and the wires can be reduced by more than 40%.

Xianwu Xing

Ching Chuen Jong

Floorplan-Driven Multivoltage High-Level Synthesis

A new structure for an exclusive-OR (XOR) gate based on the resonant-tunneling high electron mobility transistor (RTHEMT) is introduced which comprises only an RTHEMT and two FETs. Calculations are done by utilizing a new subcircuit model for simulating the RTHEMT in the SPICE simulator. Details of the design, input, and output values and margins, delay of each transition, maximum operating frequency, static and dynamic power dissipations of the new structure are discussed and calculated and the performance is compared with other XOR gates which confirm  that the presented structure has a high performance. Furthermore, to the best of authors&#39; knowledge, it has the least component count in comparison to the existing structures.

Mohammad Javad Sharifi

Davoud Bahrepour

A New XOR Structure Based on Resonant-Tunneling High Electron Mobility Transistor

Feed-forward techniques are explored for the design of high-frequency Operational
Transconductance Amplifiers (OTAs). For single-stage amplifiers, a recycling folded-cascode OTA presents twice
the GBW (197.2&#x2009;MHz versus 106.3&#x2009;MHz) and more than twice the slew rate (231.1&#x2009;V/<svg style="vertical-align:-2.29482pt;width:9.6374998px;" id="M1" height="9.6750002" version="1.1" viewBox="0 0 9.6374998 9.6750002" width="9.6374998"  xmlns="http://www.w3.org/2000/svg">
	<g transform="matrix(1.25,0,0,-1.25,0,9.675)">
		<g transform="translate(72,-64.26)">
			<text transform="matrix(1,0,0,-1,-71.95,66.6)">
				<tspan style="font-size: 12.50px; " x="0" y="0">𝜇</tspan>
			</text>

		</g>
	</g>
</svg>s versus 99.3&#x2009;V/<svg style="vertical-align:-2.29482pt;width:9.6374998px;" id="M2" height="9.6750002" version="1.1" viewBox="0 0 9.6374998 9.6750002" width="9.6374998"  xmlns="http://www.w3.org/2000/svg">
	<g transform="matrix(1.25,0,0,-1.25,0,9.675)">
		<g transform="translate(72,-64.26)">
			<text transform="matrix(1,0,0,-1,-71.95,66.6)">
				<tspan style="font-size: 12.50px; " x="0" y="0">𝜇</tspan>
			</text>

		</g>
	</g>
</svg>s) as a conventional folded cascode OTA for the same load, power consumption, and transistor dimensions. It is demonstrated that the efficiency of the recycling folded-cascode is equivalent to that of a telescopic OTA. As for multistage amplifiers, a No-Capacitor Feed-Forward (NCFF) compensation scheme which uses a high-frequency pole-zero doublet to obtain
greater than 90&#x2009;dB DC gain, GBW of 325&#x2009;MHz and better than <svg style="vertical-align:-0.17555pt;width:20.200001px;" id="M3" height="11.0375" version="1.1" viewBox="0 0 20.200001 11.0375" width="20.200001"  xmlns="http://www.w3.org/2000/svg">
	<g transform="matrix(1.25,0,0,-1.25,0,11.0375)">
		<g transform="translate(72,-63.17)">
			<text transform="matrix(1,0,0,-1,-71.95,63.39)">
				<tspan style="font-size: 12.50px; " x="0" y="0">7</tspan>
				<tspan style="font-size: 12.50px; " x="6.2515001" y="0">0</tspan>
			</text>

			<text transform="matrix(1,0,0,-1,-59.45,68.56)">
				<tspan style="font-size: 8.75px; " x="0" y="0">∘</tspan>
			</text>

		</g>
	</g>
</svg> phase margin is discussed. The settling-time- of the NCFF topology can be faster than that of OTAs with Miller compensation. Experimental results for the recycling folded-cascode OTA fabricated in TSMC 0.18&#x2009;<svg style="vertical-align:-2.29482pt;width:9.6374998px;" id="M4" height="9.6750002" version="1.1" viewBox="0 0 9.6374998 9.6750002" width="9.6374998"  xmlns="http://www.w3.org/2000/svg">
	<g transform="matrix(1.25,0,0,-1.25,0,9.675)">
		<g transform="translate(72,-64.26)">
			<text transform="matrix(1,0,0,-1,-71.95,66.6)">
				<tspan style="font-size: 12.50px; " x="0" y="0">𝜇</tspan>
			</text>

		</g>
	</g>
</svg>m CMOS, and results of the NCFF demonstrate the efficiency and feasibility of the feed-forward schemes.

Rida Assaad

Jose Silva-Martinez

Recent Advances on the Design of High-Gain Wideband Operational Transconductance Amplifiers

In recent years, subthreshold operation has gained a lot of attention due to ultra low-power consumption in applications requiring low to medium performance. It has also been shown that by optimizing the device structure, power consumption of digital subthreshold
                   logic can be further minimized while improving its performance. Therefore, subthreshold circuit design is very promising for future ultra low-energy sensor applications as well as high-performance parallel processing. This paper deals with various device and circuit design challenges associated with the state of the art in optimal digital subthreshold circuit design and reviews device design methodologies and circuit topologies for optimal digital subthreshold operation. This paper identifies the suitable candidates for subthreshold operation at device and circuit levels for optimal subthreshold circuit design and provides an effective roadmap for digital designers interested to work with ultra low-power applications.

Ramesh Vaddi

S. Dasgupta

R. P. Agarwal

Device and Circuit Design Challenges in the Digital Subthreshold 
                        Region for Ultralow-Power Applications

This paper presents a network-on-chip (NoC)
with flexible infrastructure based on dynamic wormhole packet
identity management. The NoCs are developed based on a VHDL
approach and support the design flexibility. The on-chip router
uses a wormhole packet switching method with a synchronous
parallel pipeline technique. Routing algorithms and dynamic
wormhole local packet identity (ID-tag) mapping management are
proposed to support a wire sharing methodology and an ID slot
division multiplexing technique. At each communication link, flits
belonging to the same message have the same local ID-tag, and the
ID-tag is updated before the packet enters the next communication
link by using an ID-tag mapping management unit. Therefore, flits
from different messages can be interleaved, identified, and routed
according to their allocated ID slots. Our NoC guarantees in order
and lossless message delivery.

Faizal A. Samman

Thomas Hollstein

Manfred Glesner

Networks-On-Chip Based on Dynamic Wormhole Packet Identity Mapping Management

About this journal

Journal profile

Meet the editorial board

Editor spotlight

Submit your proposal

Do you think there is an emerging area of research that really needs to be highlighted? Or an existing research area that has been overlooked or would benefit from deeper investigation? Raise the profile of a research area by leading a Special Issue.

VLSI Design