VLSI Design

Table of Contents

  • VLSI Design -
  • Special Issue
  • - Volume 8
  • - Article ID 024985

Electron Transport In One-Dimensional Magnetic Superlattices

Zhen-Li Ji | D. W. L. Sprung
  • VLSI Design -
  • Special Issue
  • - Volume 8
  • - Article ID 067609

Electrostatic Formation of Coupled Si/SiO2 Quantum Dot Systems

Per Hyldgaard | Henry K. Harbury | Wolfgang Porod
  • VLSI Design -
  • Special Issue
  • - Volume 2
  • - Article ID 013748

Pioneer: A New Tool for Coding of Multi-Level Finite State Machines Based on Evolution Programming

S. Muddappa | R. Z. Makki | ... | S. Isukapalli
  • VLSI Design -
  • Special Issue
  • Volume 14
  • - Article ID 918214

Term Trees in Application to an Effective and Efficient ATPG for AND–EXOR and AND–OR Circuits

Lech Jóźwiak | Aleksander Ślusarczyk | Marek Perkowski
  • VLSI Design -
  • Special Issue
  • - Volume 8
  • - Article ID 069743

Modeling of Thermal Effects in Semiconductor Structures

Christopher M. Snowden
  • VLSI Design -
  • Special Issue
  • - Volume 13
  • - Article ID 027920

Efficient Silicon Device Simulation with the Local Iterative Monte Carlo Method

Jürgen Jakumeit | Torsten Mietzner | Umberto Ravaioli
  • VLSI Design -
  • Special Issue
  • - Volume 1
  • - Article ID 042309

Coverage of Node Shorts Using Internal Access and Equivalence Classes

Warren H. Debany
  • VLSI Design -
  • Special Issue
  • - Volume 10
  • - Article ID 050892

Hierarchy Restructuring for Hierarchical LVS Comparison

Wonjong Kim | Hyunchul Shin
  • VLSI Design -
  • Special Issue
  • - Volume 12
  • - Article ID 061965

A Systematic Approach to Reduce the System Bus Load and Power in Multimedia Algorithms

Koen Danckaert | Chidamber Kulkarni | ... | Vivek Tiwari
  • VLSI Design -
  • Special Issue
  • Volume 11
  • - Article ID 052658

A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop

Chua-Chin Wang | Yu-Tsun Chien | Ying-Pei Chen
  • VLSI Design -
  • Special Issue
  • Volume 3
  • - Article ID 035157

A Comparative Study of Synchronous Clocking Schemes for VLSI Based Systems

Ahmed El-Amawy | Umasankar Maheshwar
  • VLSI Design -
  • Special Issue
  • Volume 4
  • - Article ID 094696

Design and Implementation of a Low Power Ternary Full Adder

A. Srivastava | K. Venkatapathy
  • VLSI Design -
  • Special Issue
  • Volume 15
  • - Article ID 871914

A Contraction-based Ratio-cut Partitioning Algorithm

Youssef Saab
  • VLSI Design -
  • Special Issue
  • - Volume 7
  • - Article ID 084860

High Performance, Point-to-Point, Transmission Line Signaling

André Dehon | Thomas F. Knight
  • VLSI Design -
  • Special Issue
  • Volume 5
  • - Article ID 069892

High-Level Graphical Abstraction in Digital Design

Murray W. Pearson | Paul J. Lyons | Mark D. Apperley

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