The System Level Applications of Adaptive Computing (SLAAC) project is defining anopen, distributed, scalable, adaptive computing systems architecture based on a highspeednetwork cluster of heterogeneous, FPGA-accelerated nodes. Two reference implementationsof this architecture are being created. The Research Reference Platform(RRP) is a MyrinetTM cluster of PCs with PCI-based FPGA accelerators (SLAAC-1).The Deployable Reference Platform (DRP) is a Myrinet cluster of PowerPCTM nodeswith VME-based FPGA accelerators (SLAAC-2) and a commercial 6U-VME quad-PowerPC board (CSPI M2641S) serving as the carrier. A key strategy proposed forsuccessful ACS technology insertions is source-code compatibility between the RRP andDRP platforms. This paper focuses on the development of the SLAAC-1 and SLAAC-2accelerators and how the network-centric SLAAC system-level architecture has shapedtheir designs. A preliminary mapping of a Synthetic Aperture Radar/Automatic TargetRecognition (SAR/ATR) algorithm to SLAAC-2 is also discussed.

Brian  Schott

Stephen P. Crago

Robert H. Parker

Chen H. Chen

Lauretta C. Carter

Joseph P. Czarnaski

Matthew  French

Ivan  Hom

Tam  Tho

Terri  Valenti

Reconfigurable Architectures for System LevelApplications of Adaptive Computing

In this paper new methods for the transformation of a given combinational circuit into
a self-dual circuit based on the notion of a self-dual complement are investigated. The
large variety of self-dual complements can be utilized to optimize the transformed self-dual
circuit. Self-dual duplication and self-dual parity prediction are considered in
detail. As a method for the reduction of self-dual outputs, output space compaction of
self-dual outputs is considered. For the first time we also describe in this paper how a
self-dual circuit can be modified into a self-dual fault-secure circuit.

A. Dmitriev

V. Saposhnikov

Vl. Saposhnikov

M. Goessel

Vl. Moshanin

A. Morosov

New Self-dual Circuits for Error Detection and Testing

The balanced partitioning problem divides the nodes of a &#91;hyper&#93;graph into groups ofapproximately equal weight (i.e., satisfying balance constraints) while minimizing thenumber of &#91;hyper&#93;edges that are cut (i.e., adjacent to nodes in different groups). Classiciterative algorithms use the pass paradigm &#91;24&#93; in performing single-node moves &#91;16, 13&#93;to improve the initial solution. To satisfy particular balance constraints, it is usual torequire that intermediate solutions satisfy the constraints. Hence, many possible movesare rejected.Hypergraph partitioning heuristics have been traditionally proposed for andevaluated on hypergraphs with unit node weights only. Nevertheless, many real-worldapplications entail varying node weights, e.g., VLSI circuit partitioning where nodeweight typically represents cell area. Even when multilevel partitioning &#91;3&#93; is performedon unit-node-weight hypergraphs, intermediate clustered hypergraphs have varyingnode weights. Nothing prevents the use of conventional move-based heuristics whennode weights vary, but their performance deteriorates, as shown by our analysis ofpartitioning results in &#91;1&#93;.We describe two effects that cause this deterioration and propose simplemodifications of well-known algorithms to address them. Our baseline implementationsachieve dramatic improvements over previously reported results (by factors of up to 25);explicitly addressing the described harmful effects provides further improvement.Overall results are superior to those of the PROP-REXest algorithm reported in &#91;14&#93;,which addresses similar problems.

Andrew E. Caldwell

Andrew B. Kahng

Igor L. Markov

Iterative Partitioning with Varying Node Weights

Previous efforts to build hardware accelerators for VLSI layout Design Rule Checking(DRC) were hobbled by the fact that it is often impractical to build a different rulecheckingASIC each time design rules or fabrication processes change. In this paper, wepropose a configurable hardware approach to DRC. It can garner impressive speedupsover software approaches, while retaining the flexibility needed to change the rule checkeras rules or processes change.Our work proposes an edge-endpoints-based method for performing Manhattangeometry checking and a general scalable architecture for DRC. We then demonstrateour approach by applying this architecture to a set of design rules for MOSISSCN4N_SUB process. We have implemented several design rule checks within a singleXilinx XC4013 FPGA and demonstrated overall speedups in excess of 25X over softwaremethods. We have used a Compaq Pamette board to do the hardware prototyping andhave achieved a clock rate of 33 MHz.

Zhen  Luo

Margaret  Martonosi

Pranav  Ashar

An Edge-endpoint-based Configurable HardwareArchitecture for VLSI Layout Design Rule Checking

Jack  Jean

Sanjaya  Kumar

Guest Editorial

Mathematically the most difficult partitioning problem&#8211;packaging&#8211;is being considered.Its purpose is to minimize a number of partitions and to satisfy the constraints onthe number of constituent elements and external nets. To solve the problem, the OptimalCircuit Reduction Method, suggested by R. Bazylevych is being used. The optimalreduction tree to reflect the hierarchical entrance of smaller clusters into bigger ones isbeing built for the first step. At the second step we select one or more tree vertices whichbetter meet the given constraints and are the first partitions generated from. Aftercreating every new partition we eliminate its elements from the circuit and repeat theprocedure to complete all partitions. During the last stage optimization strategies toexchange some elements between the partitions are being used. Better or equivalentresults among known tests confirm the effectiveness of this method.

R. P. Bazylevych

R. A. Melnyk

O. G. Rybak

Circuit Partitioning for FPGAs by the Optimal Circuit Reduction Method

In this paper, we present an algorithm for circuit partitioning with complex resource
constraints in large FPGAs. Traditional partitioning methods estimate the capacity of
an FPGA device by counting the number of logic blocks, however this is not accurate
with the increasing diverse resource types in the new FPGA architectures. We first
propose a network flow based method to optimally check whether a circuit or a subcircuit
is feasible for a set of available heterogeneous resources. Then the feasibility
checking procedure is integrated in the FM-based algorithm for circuit partitioning.
Incremental flow technique is employed for efficient implementation. Experimental
results on the MCNC benchmark circuits show that our partitioning algorithm not only
yields good results, but also is efficient. Our algorithm for partitioning with complex
resource constraints is applicable for both multiple FPGA designs (e.g., logic emulation
systems) and partitioning-based placement algorithms for a single large hierarchical
FPGA (e.g., Actel's ES6500 FPGA family).

Huiqun  Liu

Kai  Zhu

D. F. Wong

FPGA Partitioning with Complex Resource Constraints

The tutorial introduces the partitioning with applications to VLSI circuit designs. Theproblem formulations include two-way, multiway, and multi-level partitioning, partitioningwith replication, and performance driven partitioning. We depict the modelsof multiple pin nets for the partitioning processes. To derive the optimum solutions,we describe the branch and bound method and the dynamic programming methodfor a special case of circuits. We also explain several heuristics including the groupmigration algorithms, network flow approaches, programming methods, Lagrangemultiplier methods, and clustering methods. We conclude the tutorial with researchdirections.

Sao-Jie  Chen

Chung-Kuan  Cheng

Tutorial on VLSI Partitioning

Youssef  Saab

Delay time estimation in simulation or design verification step during a design cycle
has become more and more important as the meaning of performance prediction. This
paper proposed a delay estimation model for digital CMOS circuits, which works
in gate-level but the modeling process includes the characteristics of MOSFETs. This
model can handle the variation according to the kind of gates, input transition time,
output load(fan-out), and transistor sizes of a gate. The procedure to find the general
model was that, a delay model for CMOS inverter was extracted first, then it was
extended to other gate by converting it into an equivalent inverter. The resulting model
was evaluated and compared with SPICE simulation, which showed that the proposed
model has the accuracy of less than 5% relative error rate to the SPICE results for each
case and the speed of about 70 times faster than SPICE.

Dong-Wook Kim

Tae-Yong Choi

Delay Time Estimation Model for Large Digital CMOS Circuits

Recently a multiple-sequence test generator was presented based on two-dimensionallinear feedback shift registers (2-D LFSR). This generator can generate a set of precomputedtest vectors obtained by an ATPG tool for detecting random-pattern-resistantfaults and particular hard-to-detect faults. In addition, it can generate better randompatterns than a conventional LFSR. In this paper we describe an optimized BIST schemewhich has a configurable 2-D LFSR structure. Starting from a set of stuck-at faults anda corresponding set of test vectors detecting these faults, the corresponding test patterngenerator is determined automatically. A synthesis procedure of designing this testgenerator is presented. Experimental results show that the hardware overhead is considerablyreduced compared with 2-D LFSR generators.

Chien-In Henry Chen

Yingjie  Zhou

Configurable 2-D Linear Feedback Shift Registers for VLSI Built-in Self-test Designs

We present a new parallel sorting algorithm that uses a fixed-size sorter iteratively tosort inputs of arbitrary size. A parallel sorting architecture based on this algorithm isproposed. This architecture consists of three components, linear arrays that supportconstant-time operations, a multilevel sorting network, and a termination detection tree,all operating concurrently in systolic processing fashion. The structure of this sortingarchitecture is simple and regular, highly suitable for VLSI realization. Theoreticalanalysis and experimental data indicate that the performance of this architecture islikely to be excellent in practice.

Yanjun  Zhang

S. Q. Zheng

An Efficient Parallel VLSI Sorting Architecture

The capabilities of the conceptual link between threshold gates and sorting networksare explored by implementing some arithmetic demonstrators. In particular, both an(8 &#215; 8)-multiplier and a (15, 4) counter which use a sorter as the main building blockhave been implemented. Traditional disadvantages of binary sorters such as theirhardware intensive nature are avoided by using &#957;MOS circuits. It allows both animproving of previous results for multipliers based on a similar architecture, and toobtain a new type of counter which shows a reduced delay when compared to a conventionalimplementation.

E.  Rodr&#237;guez-Villegas

M. J. Avedillo

J. M. Quintana

G.  Huertas

A.  Rueda

&#957;MOS-based Sorter for Arithmetic Applications

We present a new scalable architecture for the realization of fully programmable rankorder filters (ROF). Capacitive Threshold Logic (CTL) gates are utilized for theimplementation of the multi-input programmable majority (voting) functions requiredin the architecture. The CTL-based realization of the majority gates used in the ROFarchitecture allows the filter rank as well as the window size to be user-programmable,using a much smaller silicon area, compared to conventional realizations of digitalmedian filters. The proposed filter architecture is completely modular and scalable, andthe circuit complexity grows only linearly with maximum window size (m) and withword length (n). A prototype of the proposed filter circuit has been designed andfabricated using double-polysilicon 0.8 &#956;m CMOS technology. Detailed post-layoutsimulations and test results of the ROF prototype circuit indicate that the newarchitecture can accommodate sampling clock rates of up to 50 MHz, corresponding toan effective data processing rate of 800 Mb/s for a very large filter with window size 63and word length of 16 bits.

&#304;.  Hatirnaz

F. K. G&#252;rkaynak

Y.  Leblebici

A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic

Parag K. Lala

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