VLSI Design

Spectral Transforms Calculation through Decision Diagrams

Genetic Spot Optimization for Peak Power Estimation in Large VLSI Circuits

Energy Efficient Signaling in Deep-submicron Technology

Design Methodology of a 32-bit Arithmetic Logic Unit with an Adaptive Leaf-cell Based Layout Technique

Timing Challenges for Very Deep Sub-Micron (VDSM) IC

An Algorithm Visualization Tool on the Reconfigurable Mesh

An Empirical Algorithm for Power Analysis in Deep Submicron Electronic Designs

Timing Analysis and Optimization for DSM IC—Guest Editorial

Power Efficient Hierarchical Scheduling for DSP Transformations

Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

An Embedded Low Transistor Count 8-bit Analog-to-digital Converter Using a Binary Searching Method

Minimizing Spurious Switching Activities with Transistor Sizing

A Parallel Residue-to-binary Converter for the Moduli Set

A Combined Coefficient Segmentation and Block Processing Algorithm for Low Power Implementation of FIR Digital Filters

COPAS: A New Algorithm for the Partial Input Encoding Problem

VLSI Design

Table of Contents

Table of Contents: 2002

Spectral Transforms Calculation through Decision Diagrams

Genetic Spot Optimization for Peak Power Estimation in Large VLSI Circuits

Energy Efficient Signaling in Deep-submicron Technology

Design Methodology of a 32-bit Arithmetic Logic Unit with an Adaptive Leaf-cell Based Layout Technique

Timing Challenges for Very Deep Sub-Micron (VDSM) IC

An Algorithm Visualization Tool on the Reconfigurable Mesh

An Empirical Algorithm for Power Analysis in Deep Submicron Electronic Designs

Timing Analysis and Optimization for DSM IC—Guest Editorial

Power Efficient Hierarchical Scheduling for DSP Transformations

Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

An Embedded Low Transistor Count 8-bit Analog-to-digital Converter Using a Binary Searching Method

Minimizing Spurious Switching Activities with Transistor Sizing

A Parallel Residue-to-binary Converter for the Moduli Set

A Combined Coefficient Segmentation and Block Processing Algorithm for Low Power Implementation of FIR Digital Filters

COPAS: A New Algorithm for the Partial Input Encoding Problem